-
公开(公告)号：US12001811B2
公开(公告)日：2024-06-04
申请号：US17281021
申请日：2018-10-11
申请人： TDK CORPORATION
发明人： Kuniyasu Ito , Tatsuo Shibata
CPC分类号： G06F7/5443 , G06G7/16 , G06N3/065
摘要： A multiply-accumulate calculation device includes: multiple calculation units which generates output signals by multiplying an input signal corresponding to an input value and having a rising part, a signal part, and a falling part by a weight, and output the output signals; an accumulate calculation unit configured to calculate a sum of the output signals output from the plurality of multiple calculation units; and a correction unit configured to execute correction processing for correcting the sum of the output signals on the basis of a correction value including at least one of a first value incorporated into the sum by a current flowing into variable resistors of the multiple calculation units due to the rising part of the input signal, and a second value incorporated into the sum by a current flowing into the variable resistors of the multiple calculation units due to the falling part of the input signal.
-
公开(公告)号：US11922240B2
公开(公告)日：2024-03-05
申请号：US17139226
申请日：2020-12-31
申请人： Ceremorphic, Inc.
发明人： Ryan Boesch , Martin Kraemer , Wei Xiong
摘要： A multiplier-accumulator accepts A and B digital inputs and generates a dot product P by applying the bits of the A input and the bits of the B inputs to unit elements comprised of groups of AND gates coupled to charge transfer lines through a capacitor Cu. The number of bits in the B input is a number of AND-groups and the number of bits in A is the number of AND gates in an AND-group. Each unit element receives one bit of the B input applied to all of the AND gates of the unit element, and each unit element having the bits of A applied to each associated AND gate input of each unit element. The AND gates are coupled to charge transfer lines through a capacitor Cu, and the charge transfer lines couple to binary weighted charge summing capacitors which sum and scale the charges from the charge transfer lines, the charge coupled to an analog to digital converter which forms the dot product output. The charge transfer lines may span multiple unit elements.
-
公开(公告)号：US20230409843A1
公开(公告)日：2023-12-21
申请号：US18035601
申请日：2021-10-29
发明人： Hiroshi Yoshida , Jun Okuno , Hiroki Koga , Yusuke Shuto , Takeo Tsukamoto
IPC分类号： G06G7/16
CPC分类号： G06G7/16
摘要： The present disclosure relates to a semiconductor device capable of reducing energy consumption.
Provided is a semiconductor device including: an input unit that inputs a charge; a computing unit that accumulates a charge from the input unit and performs an arithmetic operation; and an output unit that detects and outputs the charge accumulated in the computing unit, in which the computing unit includes an accumulation unit to which a plurality of pair units, each of which is a pair of the input unit and a gate unit, is connected, each of the plurality of pair units makes a charge input from the input unit to the accumulation unit variable, and the accumulation unit accumulates a charge input from each of the connected plurality of pair units. The present disclosure is, for example, applicable to an analog computing device.-
公开(公告)号：US11836461B2
公开(公告)日：2023-12-05
申请号：US17425055
申请日：2020-01-17
发明人： Hiroshi Yoshida
摘要： An arithmetic apparatus includes input lines and multiply-accumulate devices. An electrical signal for an input value is input into each of the input lines within a predetermined input period. Multiplication units include a positive weight multiplication unit that generates a positive weight charge for a product value obtained by multiplying the input value by a positive weight value and/or a negative weight multiplication unit that generates a negative weight charge for a product value obtained by multiplying the input value by a negative weight value. They are configured such that a positive weight ratio that is a ratio of a sum total of the positive weight values to a sum total of absolute values of the weight values is any ratio of 0% to 100%. An output unit of the multiply-accumulate device accumulates the generated weight charges to output a multiply-accumulate signal representing a sum of the product values.
-
公开(公告)号：US11803354B2
公开(公告)日：2023-10-31
申请号：US17178592
申请日：2021-02-18
发明人： Seonghwan Cho , Hyuk Jin Lee , Kyung Hyun Kim , Jin-O Seo
CPC分类号： G06F7/5443 , G06G7/16 , G06F2207/4814
摘要： A MAC operating device comprising a plurality of operation circuits respectively including an operation capacitor and a plurality of switches; and a division capacitor, wherein one end of the operation capacitor is respectively connected to a first operation switch connected to an input terminal and a first reset switch connected to a ground terminal, and the other end of the operation capacitor is connected to both a second operation switch connected to a division capacitor and a second reset switch connected to the ground terminal is provided.
-
公开(公告)号：US20230325650A1
公开(公告)日：2023-10-12
申请号：US17847491
申请日：2022-06-23
发明人： Hieu Van Tran , THUAN VU , STANLEY HONG , STEPHEN TRINH , MARK REITEN
摘要： Numerous examples are disclosed of an artificial neural network that comprises vector-by-matrix multiplication arrays utilizing analog outputs. In one example, a system comprises a vector by matrix multiplication array comprising a plurality of non-volatile memory cells arranged in rows and columns; and an output circuit to receive a respective neuron current from respective columns of the vector by matrix multiplication array and to generate a respective output voltage, the output circuit comprising a neuron scalar to generate a scaled current from the received respective neuron current, and a current-to-voltage converter to convert the scaled current into the respective output voltage.
-
公开(公告)号：US11782680B2
公开(公告)日：2023-10-10
申请号：US17258309
申请日：2019-07-05
申请人： Sony Corporation
CPC分类号： G06F7/57 , G06F7/5443 , G06G7/16 , G06G7/161 , G06N3/065 , H03K17/30 , H03K19/0944
摘要： An arithmetic logic unit according to an embodiment of the present technology includes: a plurality of input lines; and a multiply-accumulate operation device. Electrical signals are input to the plurality of input lines. The multiply-accumulate operation device includes a pair of output lines, a plurality of multiplication units including a weight unit that generates, on the basis of the electrical signals input to the plurality of input lines, charges corresponding to multiplication values obtained by multiplying signal values represented by the electrical signals by weight values, a holding unit that holds a binary state, and a switch unit that outputs, on the basis of the held binary state, the charges generated by the weight unit to one of the pair of output lines, an accumulation unit that accumulates the charges output to the pair of output lines by the plurality of multiplication units, and an output unit that outputs, on the basis of the accumulated charges, a multiply-accumulate signal representing a sum of the multiplication values.
-
公开(公告)号：US20230050386A1
公开(公告)日：2023-02-16
申请号：US17886089
申请日：2022-08-11
发明人： Yanmei GUO , Zhen ZHU , Yuehui LI , Xiaoru GAO , Yihui CHEN , Haifeng MIAO , Rulong JIANG
摘要： An operation circuit and a chip pertaining to the field of integrated circuit design technology are disclosed by the present application. The circuit includes a capacitor charging/discharging module and an error amplification module electrically connected to the capacitor charging/discharging module. The capacitor charging/discharging module is configured to receive a first signal and a third signal that are external to the capacitor charging/discharging module and to output a feedback signal. The error amplification module is configured to receive the feedback signal and a second signal that is external to error amplification module and to output, based on the received feedback and second signals, a target signal to the capacitor charging/discharging module. In a steady state, values of the target, first, second and third signals satisfy a predefined mathematical relationship.
-
公开(公告)号：US11449689B1
公开(公告)日：2022-09-20
申请号：US16730446
申请日：2019-12-30
申请人： Ali Tasdighi Far
发明人： Ali Tasdighi Far
摘要： Analog multipliers can perform signal processing with approximate precision asynchronously (clock free) and with low power consumptions, which can be advantageous including in emerging mobile and portable artificial intelligence (AI) and machine learning (ML) applications near or at the edge and or near sensors. Based on low cost, mainstream, and purely digital Complementary-Metal-Oxide-Semiconductor (CMOS) manufacturing process, the present invention discloses embodiments of current-mode analog multipliers that can be utilized in multiply-accumulate (MAC) signal processing in end-application that require low cost, low power consumption, (clock free) and asynchronous operations.
-
公开(公告)号：US20220164551A1
公开(公告)日：2022-05-26
申请号：US17440835
申请日：2020-03-12
发明人： Hiroshi Yoshida
摘要： An arithmetic apparatus includes input line pairs and a multiply-accumulate device. A signal pair is input to the input line pairs within an input period. The multiply-accumulate device includes multiplication units, an accumulation unit, a charging unit, and an output unit. The multiplication units generate a positive weight charge and a negative weight charge. The accumulation unit accumulates the positive weight charge and the negative weight charge. The charging unit charges the accumulation unit after the input period. The output unit performs, after charging starts, threshold determination using a predetermined threshold value on a voltage of the accumulation unit, to thereby output a positive multiply-accumulate signal representing a sum of positive weight product values and a negative multiply-accumulate signal representing a sum of negative weight product values.
-
-
-
-
-
-
-
-
-
搜索结果
782 条记录 (耗时 0.025 秒)
