公开(公告)号：US12019582B2

公开(公告)日：2024-06-25

申请号：US17569081

申请日：2022-01-05

申请人： SAPEON KOREA INC.

发明人： Seung Rok Jung

IPC分类号： G06F15/80 ,  G06F11/07 ,  G06F15/163

CPC分类号： G06F15/8046 ,  G06F11/07 ,  G06F15/163

摘要： A systolic array device according an embodiment includes a plurality of processing units arranged in a matrix form of M by N (M and N are natural numbers). Each of the processing units includes: a processing element configured to perform a predetermined processing based on data received from a processing unit arranged adjacent to one side of the corresponding processing unit to output a result thereof; and a transfer part configured to perform one of an operation of transferring the received data to another processing unit arranged adjacent to the other side of the corresponding processing unit and an operation of transferring the result.

公开(公告)号：US20230334355A1

公开(公告)日：2023-10-19

申请号：US18138989

申请日：2023-04-25

申请人： 1372934 B.C. Ltd.

发明人： Andrew Douglas King ,  Alexandre Fréchette ,  Evgeny A. Andriyash ,  Trevor Michael Lanting ,  Emile M. Hoskinson ,  Mohammad H. Amin

IPC分类号： G06N10/00 ,  G06F15/163

CPC分类号： G06N10/00 ,  G06F15/163

摘要： Degeneracy in analog processor (e.g., quantum processor) operation is mitigated via use of floppy qubits or domains of floppy qubits (i.e., qubit(s) for which the state can be flipped with no change in energy), which can significantly boost hardware performance on certain problems, as well as improve hardware performance for more general problem sets. Samples are drawn from an analog processor, and devices comprising the analog processor evaluated for floppiness. A normalized floppiness metric is calculated, and an offset added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.

公开(公告)号：US20230089122A1

公开(公告)日：2023-03-23

申请号：US17799840

申请日：2021-11-15

申请人： LG ENERGY SOLUTION, LTD.

发明人： Yee-Gahng SONG

IPC分类号： H01M10/42 ,  G06F15/163

摘要： A BMS managing apparatus including a master BMS and a plurality of slave BMSs, and includes: a master BMS for sending an NV (non-volatile) value confirmation request to the plurality of slave BMSs, and sending a uniformization request to the plurality of slave BMSs based on whether a source ID is set, when a response to the NV value confirmation request is received from the plurality of slave BMSs; and a plurality of slave BMSs for sending each NV value to the master BMS when the NV value confirmation request is received from the master BMS, setting a representative BMS and a target BMS based on the plurality of NV values, setting the representative BMS or a slave BMS corresponding to the source ID as a source BMS according to the uniformization request received from the master BMS, and updating an NV value of the target BMS according to an NV value of the source BMS.

公开(公告)号：US11474970B2

公开(公告)日：2022-10-18

申请号：US16726492

申请日：2019-12-24

申请人： Meta Platforms Technologies, LLC

发明人： Jun Wang ,  Neeraj Upasani ,  Wojciech Stefan Powiertowski ,  Drew Eric Wingard ,  Gregory Edward Ehmann ,  Marco Brambilla ,  Minli Lin ,  Miguel Angel Guerrero

IPC分类号： G06F15/163 ,  H04N13/344 ,  G06F15/173 ,  G06F15/167

摘要： The disclosure describes techniques for interrupt and inter-processor communication (IPC) mechanisms that are shared among computer processors. For example, an artificial reality system includes a plurality of processors; an inter-processor communication (IPC) unit comprising a register, wherein the IPC unit is configured to: receive a memory access request from a first processor of the processors, wherein the memory access request includes information indicative of a hardware identifier (HWID) associated with the first processor; determine whether the HWID associated with the first processor matches an HWID for the register of the IPC unit; and permit, based on determining that the HWID associated with the first processor matches the HWID for the register of the IPC unit, the memory access request to indicate a communication from the first processor to at least one other processor.

公开(公告)号：US11410026B2

公开(公告)日：2022-08-09

申请号：US16191906

申请日：2018-11-15

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Woo-Yeong Cho ,  Seong-Il O ,  Hak-Soo Yu ,  Min-Su Choi

IPC分类号： G06N3/063 ,  G06N3/04 ,  H01L27/24 ,  H01L25/065 ,  G06F15/163

摘要： Provided are a neuromorphic circuit having a three-dimensional stack structure and a semiconductor device including the neuromorphic circuit. The semiconductor device includes a first semiconductor layer including one or more synaptic cores, each synaptic core including neural circuits arranged to perform neuromorphic computation. A second semiconductor layer is stacked on the first semiconductor layer and includes an interconnect forming a physical transfer path between synaptic cores. A third semiconductor layer is stacked on the second semiconductor layer and includes one or more synaptic cores. At least one through electrode is formed, through which information is transferred between the first through third semiconductor layers. Information from a first synaptic core in the first semiconductor layer is transferred to a second synaptic core in the third semiconductor layer via the one of more through electrodes and an interconnect of the second semiconductor layer.

公开(公告)号：US11341087B2

公开(公告)日：2022-05-24

申请号：US15576680

申请日：2016-05-24

申请人： DISPLAYLINK (UK) LIMITED

发明人： Robin Alexander Cawley ,  Colin Skinner ,  Eric Kenneth Hamaker

IPC分类号： G06F15/80 ,  G06F9/38 ,  G06F15/163 ,  G06F13/42

摘要： A heterogeneous multi-core integrated circuit comprising two or more processors, at least one of the processors being a general purpose CPU and at least one of the processors being a specialized hardware processing engine, the processors being connected by a processor local bus on the integrated circuit, wherein the general purpose CPU is configured to generate a first instruction for an atomic operation to be performed by a second processor, different from the general purpose CPU, the first instruction comprising an address of the second processor and a first command indicating a first action to be executed by the second processor, and transmit the first instruction to the second processor over the processor local bus. The first command may include the first action, or may be a descriptor of the first action or a pointer to where the first action may be found in a memory.

公开(公告)号：US11262992B2

公开(公告)日：2022-03-01

申请号：US16688744

申请日：2019-11-19

申请人： Huawei Technologies Co., Ltd.

发明人： Jian Chen ,  Hong Zhou ,  Xinyu Hu ,  Hongguang Guan ,  Xiaojun Zhang

IPC分类号： G06F8/41 ,  G06F9/38 ,  G06F9/455 ,  G06F15/163

摘要： A hardware acceleration method includes: obtaining compilation policy information and a source code, where the compilation policy information indicates that a first code type matches a first processor and a second code type matches a second processor, analyzing a code segment in the source code according to the compilation policy information, determining a first code segment belonging to the first code type or a second code segment belonging to the second code type, compiling the first code segment into a first executable code, sending the first executable code to the first processor, compiling the second code segment into a second executable code, and sending the second executable code to the second processor.

公开(公告)号：US20210044745A1

公开(公告)日：2021-02-11

申请号：US16965132

申请日：2019-03-08

申请人： Samsung Electronics Co., Ltd.

发明人： Jihwan PARK

IPC分类号： H04N5/232 ,  H04N5/33 ,  H04N5/225 ,  G06F15/163

摘要： An electronic device, according to various embodiments, comprises: one or more image sensors; a first processor electrically connected to at least one of the one or more sensors via a first interface and including a first functional processing circuit and a second functional processing circuit capable of processing first output information of the first functional processing circuit; a second processor electrically connected to at least one of the one or more image sensors via a second interface; a third interface for connecting the first functional processing circuit and the second processor to transfer the first output information of the first functional processing circuit to the second processor; and a fourth interface for connecting the second functional processing circuit and the second processor to transfer second output information of the second processor to the second functional processing circuit. Various other embodiments are possible.

公开(公告)号：US20200302090A1

公开(公告)日：2020-09-24

申请号：US16897564

申请日：2020-06-10

申请人： Coherent Logix, Incorporated

发明人： Michael B. Doerr ,  Carl S. Dobbs ,  Michael B. Solka ,  Michael R. Trocino ,  David A. Gibson

IPC分类号： G06F21/71 ,  G06F15/163 ,  G06F15/76 ,  G06F15/167 ,  G06F15/173 ,  G06F9/4401 ,  G06F15/177 ,  G06F21/57

摘要： Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.

公开(公告)号：US10725667B2

公开(公告)日：2020-07-28

申请号：US15874322

申请日：2018-01-18

申请人： SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

发明人： Jaejin Lee ,  Gangwon Jo

IPC分类号： G06F3/06 ,  G06F15/163 ,  G06F15/167 ,  G06F12/08 ,  G06F12/14

摘要： Disclosed herein are a method of transferring data in a parallel system including a main device and at least one accelerator, and a parallel system for performing the method. The method of transferring data in a heterogeneous system including a main device and at least one accelerator includes: turning off a write permission for a first main memory area corresponding to a first accelerator memory area where input data for a computation task is stored; performing the computation task by using the at least one accelerator; and turning off a read permission for a second main memory area corresponding to a second accelerator memory area where output data for the computation task is stored, in the state in which data of the second accelerator memory area has not been transferred to the second main memory area.