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    INTERNAL ERROR CORRECTION FOR MEMORY DEVICES
    1.
    发明申请
    INTERNAL ERROR CORRECTION FOR MEMORY DEVICES 有权

    公开(公告)号：US20250068515A1

    公开(公告)日：2025-02-27

    申请号：US18941943

    申请日：2024-11-08

    Applicant: Lodestar Licensing Group LLC

    Inventor： Aaron P. Boehm ,  Scott E. Schaefer

    IPC: G06F11/10 ,  G06F11/07 ,  G06F11/30

    Abstract: Methods, systems, and devices for internal error correction for memory devices are described. A memory device may perform a read operation at a memory array having a data partition and an error check partition and may obtain a first set of bits from the data partition and a second set of bits from the error check partition. The memory device may determine a first error detection result based on a value of a determined syndrome. The memory device may obtain a parity bit from the first set of bits and determine a second error detection result based on a comparison of the parity bit with a second function of the subset of the first set of bits. The memory device may transmit the first set of bits to a host device based at least in part on the first and second error detection results.

    CIRCUIT FOR STATUS MONITORING, AND FAULT RECOVERY AND ISOLATION FOR INTER-INTEGRATED CIRCUIT (I2C) BUS, AND METHOD IMPLEMENTED BY THE SAME
    2.
    发明申请
    CIRCUIT FOR STATUS MONITORING, AND FAULT RECOVERY AND ISOLATION FOR INTER-INTEGRATED CIRCUIT (I2C) BUS, AND METHOD IMPLEMENTED BY THE SAME 有权

    公开(公告)号：US20250068503A1

    公开(公告)日：2025-02-27

    申请号：US18753786

    申请日：2024-06-25

    Applicant: Alpha Networks Inc.

    Inventor： Peng-Fei Song ,  Xiao-Gang Luo

    IPC: G06F11/07

    Abstract: A circuit for status monitoring, and fault recovery and isolation for an I2C bus is provided. The I2C bus is electrically connected to a master device and a plurality of slave devices. Each of the slave devices has an address. The circuit includes a receiver unit, a decoder unit, and a troubleshooting unit. The receiver unit can receive a data signal and a clock signal that are transmitted from the master device to the I2C bus. The decoder unit is configured to obtain address information and a read/write bit based on the data signal and the clock signal. The troubleshooting unit is configured to, when the troubleshooting unit determines that a target slave device is malfunctioning based on the data signal, the clock signal, and the read/write bit, identify the target slave device based on the address information, and perform a troubleshooting operation on the target slave device.

    METHODS AND APPARATUSES FOR SELECTING FAULT MANAGEMENT MODELS
    3.
    发明申请
    METHODS AND APPARATUSES FOR SELECTING FAULT MANAGEMENT MODELS 有权

    公开(公告)号：US20250068495A1

    公开(公告)日：2025-02-27

    申请号：US18688459

    申请日：2021-09-02

    Applicant: Telefonaktiebolaget LM Ericsson (publ)

    Inventor： Chunyan FU ,  Catherine TRUCHAN

    IPC: G06F11/07 ,  G06F8/60

    Abstract: Embodiments described herein provide methods and apparatuses for selecting Nnext Fault Management Models, FMMs, where Nnext is an integer value, to run at an edge site in a cloud system during an ith time period. A method in a Fault Management System, FMS includes: in a deployment agent, DA: selecting the Nnext FMMs from a first set of FMMs based at least in part on respective probability functions associated with each of the first set of FMMs, wherein each respective probability function indicates how likely a fault associated with the respective FMM is to occur as a function of time; and initiating running of the Nnext FMMs at the edge site during the ith time period.

    Circuit interrupt device fault duration monitor
    5.
    发明授权
    Circuit interrupt device fault duration monitor 有权

    公开(公告)号：US12235718B2

    公开(公告)日：2025-02-25

    申请号：US18227232

    申请日：2023-07-27

    Applicant: Schneider Electric USA, Inc.

    Inventor： Collin Richard Fischels ,  Juan Ignacio Melecio Ramirez ,  Adrian Abdala Rendon Hernandez ,  Kenneth Riehl

    IPC: G06F11/07 ,  G06F11/32

    Abstract: Methods/systems for monitoring fault duration in circuit interrupt devices perform edge detection using a second time derivative of a current or voltage waveform. The second derivative reveals peaks that may be used to establish starting and ending times for the fault duration. In some embodiments, the second derivatives are derived only for portions of the waveform within time windows that enclose the fault duration starting and ending times, respectively. The above arrangement provides a consistent way of determining durations of transitory events, such as durations of faults, and the like, that does not rely on waveform zero-crossings. The duration determinations may be implemented locally within a device, and/or the device may acquire and transfer underlying waveform data to an external system for the duration determinations. Data from multiple devices may be collected over time for analysis and modeling to provide remote support and monitoring of local devices via digital twins.

    Dynamic Management of Data Centers
    7.
    发明申请
    Dynamic Management of Data Centers 有权

    公开(公告)号：US20250060807A1

    公开(公告)日：2025-02-20

    申请号：US18922094

    申请日：2024-10-21

    Applicant: Cerner Innovation, Inc.

    Inventor： Karthikeyan Sukumaran ,  Sravan Kumar Anumula ,  Rakesh Reddy Yarragudi ,  Manipal Reddy Thoomukunta ,  Deepak Kumar Jain

    IPC: G06F1/3287 ,  G06F1/28 ,  G06F1/30 ,  G06F11/07 ,  G06F11/30

    Abstract: Computerized systems and methods are provided to intelligently and dynamically manage a data center comprising at least one server and at least one central manager. The central manager is programmed to access the at least one server on a predetermined schedule to determine whether at least one application is functioning properly by determining a functionality level. Alternatively, the central manager determines whether the at least one server is actively used by determining an activity level for the server. Based on the central manager's determinations, the system dynamically adjusts the power level of the server, resulting in reduced power consumption and a reduction in wasted resources and unnecessary processing power in the management of servers in a data center.

    Erroneous select die access (SDA) detection
    8.
    发明授权
    Erroneous select die access (SDA) detection 有权

    公开(公告)号：US12229062B2

    公开(公告)日：2025-02-18

    申请号：US17823432

    申请日：2022-08-30

    Applicant: Micron Technology, Inc.

    Inventor： Yang Lu ,  Creston M. Dupree ,  Kang-Yong Kim

    IPC: G06F13/16 ,  G06F11/07

    Abstract: Described apparatuses and methods relate to erroneous select die access (SDA) detection for a memory system. A memory system may include a memory controller and a memory device that are capable of implementing an SDA protocol that enables selective memory die access to multiple memory devices that couple to a command bus. A memory device can include logic that determines if signaling that conflicts with the SDA protocol is detected. If it is determined that conflicting signaling is detected, the logic may provide an indication of the conflicted signaling. In doing so, the erroneous SDA detection described herein may reduce the likelihood of a memory device erroneously masking memory dice, thereby limiting the memory device from exhibiting unexpected, and in some cases, dangerous behavior.

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