Abstract:
A relay matrix which constitutes an array of switches providing connection points between a set of "horizontal" inputs and a set of "vertical" outputs, has n relays per column disposed in p columns. Each relay column is associated with a register which fulfills the functions of controlling and storing the state of the relays of the column. The invention can be applied to switching systems and in particular to automatic telecommunication exchanges.
Abstract:
Disclosed is a crosspoint matrix applicable for use in telecommunications switching networks. Each crosspoint includes a silicon controlled rectifier or semi-conductor thyristor plus a suitable gating member. A marking signal of voltage higher than a reference voltage suitably marks a selected conductor of one multiple. A voltage more negative than that of a second reference of the other multiple suitably biases a conductor of the other multiple. Concurrently therewith, a triggering signal is transmitted to the gate of the biased crosspoint completing a path across the matrix. The threshold or reference voltage levels used are considerably separated from the voltage level band used in passing information across a triggered crosspoint, thus resulting in no interference between crosspoints.
Abstract:
A communication switching network having semiconductor crosspoint elements defining unbalanced transmission paths therethrough wherein the effects of loss variations and crosstalk are substantially reduced by deliberately mismatching the impedances at opposite ends of each crosspoint path as seen from the crosspoint so that signal transmission through the crosspoint involves relatively large current variations with only very small voltage variations.
Abstract:
A thyristor switching network is disclosed in which the switching network control provides both crosspoint audit and centralized control capabilities. The switching network control circuit contains three signal generators each of which generates a particular control signal when enabled. A distribution circuit is also provided to connect each of the signal generators to a corresponding terminal of a selected thyristor crosspoint element. In this manner, the signal generators directly control the voltage appearing at any terminal of any crosspoint element and can be used to turn on, turn off, or audit the busy/idle status of any selected thyristor crosspoint element. Also, the thyristor crosspoints are switched on in the zero voltage mode and the dV/dt across the selected thyristor crosspoint element is controlled by the signal generators to eliminate false firing of the thyristor crosspoints.
Abstract:
A telephone private switching equipment of the space-division operated type comprises a matrix of electronic switch cross-points each made of a single controllable two-state member connected across a conversation conductor of a row and a conversation conductor of a column of the matrix and having a trigger terminal connected through unidirectional members to both a cross-point activation conductor of this row and a cross-point activation conductor of this column, each row and each column comprising only these two conductors. Each column of the matrix is controlled from a cross-point selection control unit capable of applying trigger pulses to the cross-point activation conductor of the column and service voltages and currents to the conversation conductor of the column. Each subscriber's line circuit of the equipment includes a two-wire to one-wire converter the one-wire terminal of which is connected to the conversation conductor of a row and includes means capable of applying periodical pulses to the cross-point activation conductor of this row. Each external network line connecting circuit of the equipment is connected by a one-wire conversation lead to the conversation conductor of a row comprising only a single cross-point of the matrix.
Abstract:
An arrangement for establishing communication paths through a plurality of serially connected thyristors comprising a first and last thyristor, is disclosed. Each thyristor comprises a main conduction path terminating in a first and second main conduction electrode and a control path between the first electrode and a gate electrode. The second main conduction electrode of each thyristor, except the last, is connected to the first main conduction electrode of a subsequent thyristor. To establish a path, a marking potential is applied to the first main conduction electrode of the first thyristor and gate currents, equal to or greater than the thyristor holding currents, are produced in the control paths of the thyristors in sequence and overlapped in time from the first to the last. A hold current is then produced in the second main conduction electrode of the last thyristor and the gate currents are terminated. Additionally, a gate current applied to a given thyristor can be terminated after the gate current of a succeeding device is flowing in the main conduction path of the given thyristor.
Abstract:
A crossoint switching circuit in which the transmission paths through the circuit are compensated such that the resistance from any input to any output is equal to the resistance from any other input to any other output. This is accomplished by varying the resistance of the metallization in the circuit according to a prescribed method. The varying of the metallization resistance is accomplished by varying the width and length of metallization from the output or input package pins to the circuit. This width variation either adds or reduces resistance to the particular switching path indicated by the prescribed method. The prescribed method entails ascertaining that set of transmission paths having a maximum of resistance between inputs and outputs, and thereafter systemmatically adding resistance to other transmission paths to bring their resistances up to this maximum without adding to the maximum already established. This is accomplished by first compensating those circuit paths having resistances next highest to the ascertained maximum. Thereafter all transmission paths are compensated in descending order. If there is no possibility of raising the resistance of a particular transmission path to the ascertained maximum without raising another transmission path resistance past the ascertained maximum, then the resistance of this particular transmission path is raised to the ascertained maximum which raises certain other transmission paths past the ascertained maximum by a certain amount. This certain amount if then added to all paths not affected by the above addition, such that a minimum resistance spread is achieved between the possible paths in the switching circuit network.
Abstract:
A SWITCHING APPARATUS INCLUDES AN ELECTRONIC CROSSPOINT NETWORK FOR PROVIDING FULL ELECTRONIC CONNECTION OR DISCONNECTION BETWEEN AT LEAST TWO POINTS WHOSE INTERCONNECTION PROVIDES THE PARTICULAR CROSSPOINT. THE NETWORK HAS AN OPEN CIRCUIT CONDITION, IN WHICH A VERY HIGH OFF IMPEDANCE IS PROVIDED, AND A CLOSED CIRCUIT CONDITION, IN WHICH A VERY LOW ON IMPEDANCE IS PROVIDED. THE NETWORK INCLUDES AT LEAST TWO SERIES CONNECTED SEMICONDUCTOR BRANCHES AND A THIRD PARALLEL CONNECTED SEMICONDUCTOR BRANCH, WHICH IS COUPLED TO GROUND, CONNECTED IN BETWEEN. IN THE OPEN CIRCUIT CONDITION, THE SERIES BRANCHES DO NOT CONDUCT AND THE PARALLEL BRANCH DOES, PROVIDING A SHORT TO GROUND, WHEREAS, IN THE CLOSED CIRCUIT CONDITION, THE OPPOSITE OCCURS, PROVIDING AN OPEN CIRCUIT TO GROUND. THE PARALLEL BRANCH IS CONTROLLED IN ACCORDANCE WITH THE DESIRED CROSSPOINT SWITCHING FUNCTION PROVIDED VIA A LOGIC NETWORK. IF DESIRED, TWO SUCH CROSSPOINT NETWORKS MAY BE COUPLED TOGETHER IN A TWO-WIRE CIRCUIT TO SIMULTANEOUSLY CONTROL TWO CROSSPOINTS. THE CROSSPOINT NETWORK IS PREFERABLY UTILIZED TO INTERCONNECT POINTS TO WHICH SIGNALS, SUCH AS TELEPHONE SPEECH SIGNALS, ARE APPLIED, A PLURALITY OF SUCH NETWORKS BEING PROVIDED IN THE MATRIX ARRAYS OF A SPACE-DIVISION TELEPHONE SWITCHING NETWORK.
Abstract:
In a semiconductor speech path at least a crosspoint element for forming a unitary matrix is formed on a semiconductor chip. The interconnections between the crosspoint elements and the matrix wirings are made on a ceramic wiring plate. By mounting a plurality of semiconductor chips on the ceramic wiring plate by face-down bonding, unitary matrix arrays are formed and at the same time the whole of a matrix array is formed.A row wiring having first speech path wirings and first selection wirings and a column wiring having second speech path wirings and second selection path wirings are doubly layered on the semiconductor wiring plate, with the intervention of an insulating layer therebetween. The upper layer, except for a pedestal region, is covered with a ceramic insulating layer. Terminals for row and column wirings are arranged in dual-in-line fashion. The speech path terminals of each of the row and column wirings are symmetrically and oppositely disposed to each other. This is correspondingly applied for the selection path terminals. With such a construction, the need for the multi-layered wiring on the semiconductor chip is eliminated, and the manufacturing of chips is simplified. Also crosstalk among the row and column wiring paths on the ceramic wiring plate is lessened and the grid wiring is facilitated.