公开(公告)号：US06725387B1

公开(公告)日：2004-04-20

申请号：US09560904

申请日：2000-04-28

Applicant: Dean T. Lindsay ,  Robert D. Snyder ,  Kent A. Dickey

Inventor： Dean T. Lindsay ,  Robert D. Snyder ,  Kent A. Dickey

IPC: G06F112

CPC classification number: G06F1/12

Abstract: A method and apparatus are disclosed for improving the repeatability of a system during testing by ensuring that the machine state remains the same on every test. In particular, the system ensures that the polling block of a cross-bar chip is reset to the same point in the polling sequence and to the same port upon the start of every test. The system uses a global framing clock (“GFC”) as a common timing reference. Before executing test code, the system becomes idle and waits for a rising edge of the GFC. The system then sends a message across existing links from the monarch processor performing the test to a cache controller chip. The cache controller chip waits for a GFC edge and then sends a reset message to the cross-bar chip to reset the CSR polling block. The cross-bar chip receives the signal and resets the CSR polling block.

Abstract translation: 公开了一种用于通过确保机器状态在每次测试中保持相同的方式来提高测试期间系统的可重复性的方法和装置。 特别地，系统确保跨条形码片的轮询块在轮询序列中被重置为相同点，并且在每次测试开始时被重置到相同的端口。 系统使用全局成帧时钟（“GFC”）作为公共时序参考。 在执行测试代码之前，系统将空闲并等待GFC的上升沿。 然后，系统将从执行测试的君主处理器到高速缓存控制器芯片的现有链路发送消息。 高速缓存控制器芯片等待GFC边沿，然后将重置消息发送到交叉条芯片以重置CSR轮询块。 横杆芯片接收信号并复位CSR轮询块。

公开(公告)号：US06708135B2

公开(公告)日：2004-03-16

申请号：US10037404

申请日：2002-01-04

Applicant: Robert A. Southworth ,  Kenneth C. Volz ,  Robert C. Morris, Jr. ,  Dan S. Carroll

Inventor： Robert A. Southworth ,  Kenneth C. Volz ,  Robert C. Morris, Jr. ,  Dan S. Carroll

IPC: G06F112

CPC classification number: G04G15/00 ,  G04G15/006 ,  G06Q30/0601

Abstract: In the present invention, several timer functions (e.g. delay on make, delay on break, recycle, single shot, etc.) are expressed in terms of a series of timer subfunctions, and code segments are developed for each identified subfunction. A program of a timer is established to include a plurality of subfunction code segments and a subfunction ordering table for determining the ordering of execution for the subfunction code segments. The ordering of subfunctions of the subfunction ordering table may be selectable in accordance with a model number input received at a program builder system adapted for use in programming the programmable timer. In one embodiment, the programming method provides for reprogramming of a timer including a control circuit having a one-time programmable processor.

Abstract translation: 在本发明中，若干定时器功能（例如，延迟延迟，延迟延迟，循环，单次发射等）以一系列定时器子功能表示，并为每个识别的子功能开发代码段。 建立定时器的程序以包括多个子功能代码段和用于确定子功能代码段的执行顺序的子功能排序表。 子功能订购表的子功能的顺序可以根据在适于在可编程定时器编程中使用的程序构建器系统接收的型号输入来选择。 在一个实施例中，编程方法提供对包括具有一次性可编程处理器的控制电路的定时器的重新编程。

公开(公告)号：US06675306B1

公开(公告)日：2004-01-06

申请号：US09523449

申请日：2000-03-10

Applicant: Michael A. Baxter

Inventor： Michael A. Baxter

IPC: G06F112

CPC classification number: G06F1/12

Abstract: An apparatus for performing phase-lock in a field programmable gate array includes a phase detector configured to determine a phase difference between a carry logic oscillator signal and a reference clock signal; and a combinational circuit coupled to the phase detector, and adapted to function as a variable carry logic oscillator, and further configured to generate the carry logic oscillator signal. A method for performing phase-lock in a field programmable gate array includes: using a carry logic oscillator in a field programmable gate array to generate a carry logic oscillator signal; and determining a phase difference between the carry logic oscillator signal and a reference clock signal.

Abstract translation: 一种用于在现场可编程门阵列中执行相位锁定的装置，包括：相位检测器，被配置为确定进位逻辑振荡器信号和参考时钟信号之间的相位差; 以及组合电路，其耦合到所述相位检测器，并且适于用作可变进位逻辑振荡器，并且还被配置为产生所述进位逻辑振荡器信号。 一种用于在现场可编程门阵列中执行相位锁定的方法包括：使用现场可编程门阵列中的进位逻辑振荡器来产生进位逻辑振荡器信号; 以及确定进位逻辑振荡器信号和参考时钟信号之间的相位差。

公开(公告)号：US06662303B1

公开(公告)日：2003-12-09

申请号：US09480875

申请日：2000-01-10

Applicant: Zabih Toosky ,  Sasan Cyrusian ,  Ulrich Huewels

Inventor： Zabih Toosky ,  Sasan Cyrusian ,  Ulrich Huewels

IPC: G06F112

CPC classification number: G11B20/10009 ,  G11B5/09

Abstract: An improved write precompensation circuit. Eight phases from a PLL phase oscillator are received as inputs into a bank of four phase blenders (104). The phase blenders (104) output a 0%, 25%, 50%, or 75% interpolation to the adjacent phases. A multiplexer (110) is then used to select which of the phase outputs is used for the write precompensation.

Abstract translation: 一种改进的预预补偿电路。 接收来自PLL相位振荡器的八个相位作为四相混合器（104）的一组输入。 相位调节器（104）向相邻相输出0％，25％，50％或75％的内插。 然后，多路复用器（110）用于选择哪个相位输出用于写入预补偿。

公开(公告)号：US06658580B1

公开(公告)日：2003-12-02

申请号：US09613988

申请日：2000-07-11

Applicant: Colin Bell ,  Mike A. Sluyski

Inventor： Colin Bell ,  Mike A. Sluyski

IPC: G06F112

CPC classification number: G06F1/14 ,  H04J3/0685 ,  H04L7/0008 ,  H04L29/06 ,  H04L41/0803 ,  H04L41/082 ,  H04L41/085 ,  H04L41/0859 ,  H04L41/0863 ,  H04L41/22 ,  H04L45/50 ,  H04L69/18 ,  H05K1/14

Abstract: The present invention provides a network device including redundant, synchronous central timing subsystems (CTSs) each having a voltage controlled timing circuit for receiving a constant master voltage signal and variable slave voltage signal. Each CTS also includes a control logic circuit for selecting the constant master voltage signal for use by the voltage controlled timing circuit when the CTS is master and for selecting the variable slave voltage signal when the CTS is slave. Using a constant master voltage signal eliminates the need for a separate master oscillator in each CTS. Oscillators are typically expensive, consume significant space on the printed circuit board and have location restrictions on where they may be placed on the printed circuit board.

Abstract translation: 本发明提供了一种网络设备，其包括冗余的同步中心定时子系统（CTS），每个中间定时子系统具有用于接收恒定的主电压信号和可变从属电压信号的电压控制定时电路。 每个CTS还包括一个控制逻辑电路，用于选择恒定的主电压信号，供CST为主时由电压控制定时电路使用，并在CTS为从机时选择可变从电压信号。 使用恒定的主电压信号消除了在每个CTS中需要单独的主振荡器。 振荡器通常是昂贵的，消耗了印刷电路板上的大量空间，并且它们可能被放置在印刷电路板上的位置受到限制。

公开(公告)号：US06591307B1

公开(公告)日：2003-07-08

申请号：US09436897

申请日：1999-11-09

Applicant: Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

Inventor： Ravi Kumar Arimilli ,  James Stephen Fields, Jr. ,  Guy Lynn Guthrie ,  Jody Bern Joyner ,  Jerry Don Lewis

IPC: G06F112

CPC classification number: G06F12/0815 ,  G06F12/0813 ,  G06F12/0831

Abstract: A data processing system includes an interconnect, a plurality of nodes coupled to the interconnect that each include at least one agent, response logic within each node, and a queue. In response to snooping a transaction on the interconnect, each agent outputs a snoop response. In addition, the queue, which has an associated agent, allocates an entry to service the transaction. The response logic within each node accumulates a partial combined response of its node and any preceding node until a complete combined response for all of the plurality of nodes is obtained. However, prior to the associated agent receiving the complete combined response, the queue speculatively deallocates the entry if the partial combined response indicates that an agent other than the associated agent will service the transaction.

Abstract translation: 数据处理系统包括互连，耦合到互连的多个节点，每个节点包括至少一个代理，每个节点内的响应逻辑和队列。 响应在互连上窥探事务，每个代理输出一个侦听响应。 此外，具有关联代理的队列分配一个条目来为事务提供服务。 每个节点内的响应逻辑累积其节点和任何先前节点的部分组合响应，直到获得所有多个节点的完整组合响应。 然而，在相关联的代理接收到完整的组合响应之前，如果部分组合响应指示除了相关联的代理之外的代理将服务于该事务，则队列推测性地释放该条目。

公开(公告)号：US06587804B1

公开(公告)日：2003-07-01

申请号：US09637088

申请日：2000-08-14

Applicant: Brian Johnson ,  Brent Keeth

Inventor： Brian Johnson ,  Brent Keeth

IPC: G06F112

CPC classification number: G11C29/028 ,  G11C7/1051 ,  G11C7/1066 ,  G11C7/1078 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/50012 ,  G11C2207/2254

Abstract: A method and apparatus for calibrating a data path of a digital circuit uses an even bit pseudo-random calibration pattern. A portion of the pattern is captured in a capture period and used to predict a next arriving portion of the calibration pattern. The next arriving portion of the calibration pattern is captured and then compared to the predicted pattern in a compare period, and the result of the comparison is used to relatively time data arriving in the data path to a clocking signal which clocks in the data. The time duration of the compare period may be varied to ensure that all possible bits of the calibration pattern are used in the calibration procedure.

Abstract translation: 用于校准数字电路的数据路径的方法和装置使用偶数位伪随机校准模式。 在捕获周期中捕获图案的一部分，并用于预测校准图案的下一个到达部分。 捕获校准图案的下一个到达部分，然后在比较周期中与预测图案进行比较，并将比较结果用于到数据路径中的相对时间数据到数据中的时钟信号。 可以改变比较周期的持续时间以确保在校准过程中使用校准图案的所有可能位。

公开(公告)号：US06542999B1

公开(公告)日：2003-04-01

申请号：US09434801

申请日：1999-11-05

Applicant: Daniel Mark Dreps ,  Kevin Charles Gower ,  Frank David Ferraiolo

Inventor： Daniel Mark Dreps ,  Kevin Charles Gower ,  Frank David Ferraiolo

IPC: G06F112

CPC classification number: G06F5/06

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract translation: 实现弹性接口装置和方法。 弹性接口包括用于存储数据值流的多个存储单元，其中每个存储单元顺序地存储各组数据值的成员。 每个数据值被存储在本地时钟的预定数量的周期内。 选择电路可以耦合到存储单元以从数据流中选择相应的数据值，以存储在相应的存储单元中。 与本地时钟的目标周期上的本地时钟同步地从每个存储单元顺序地输出数据。

公开(公告)号：US06502141B1

公开(公告)日：2002-12-31

申请号：US09461679

申请日：1999-12-14

Applicant: Freeman Leigh Rawson, III

Inventor： Freeman Leigh Rawson, III

IPC: G06F112

CPC classification number: G06F1/12

Abstract: In a multi-node non-uniform memory access (NUMA) multi-processor system, a designated node synchronization processor on each node, is synchronized. Individual nodes accomplish internal synchronization of the other processors on each node utilizing well known techniques. Thus it is sufficient to synchronize one processor on each node. Node zero, a designated system node that acts as a synchronization manager, estimates the time it takes to transmit information in packet form to a particular, remote node in the system. As a result a time value is transmitted from the remote node to node zero. Node zero projects the current time on the remote node, based on the transmission time estimate and compares that with its own time and either updates its own clock to catch up with a leading remote node or sends a new time value to the other node, requiring the remote node to advance its time to catch up with that on node zero. Code on the remaining nodes is mostly passive, responding to packets coming from node zero and setting the time base value when requested. Monotonicity of the time bases is maintained by always advancing the earliest of the two time bases so as to catch up with the later one.

Abstract translation: 在多节点非均匀存储器访问（NUMA）多处理器系统中，每个节点上的指定节点同步处理器被同步。 利用众所周知的技术，个别节点在每个节点上实现其他处理器的内部同步。 因此，在每个节点上同步一个处理器就足够了。 作为同步管理器的指定系统节点的节点零估计将分组形式的信息发送到系统中特定的远程节点所花费的时间。 因此，时间值从远程节点发送到节点零。 基于传输时间估计，节点零对远程节点上的当前时间进行投影，并将其与自己的时间进行比较，并更新其自己的时钟以赶上领先的远程节点，或者向另一个节点发送新的时间值，要求 远程节点将其时间推迟到节点零上。 剩余节点上的代码主要是被动的，响应来自节点零的数据包，并在请求时设置时基值。 通过总是推进两个时间基准中的最早时间来维持时间基准的单调性，以赶上后者。

公开(公告)号：US06351821B1

公开(公告)日：2002-02-26

申请号：US09767586

申请日：2001-01-22

Applicant: Duane J. Voth

Inventor： Duane J. Voth

IPC: G06F112

CPC classification number: H04J3/0667 ,  G06F1/14

Abstract: A system for time synchronization in a computer cluster is provided. For the system of the present invention a master node sends a SYNC message including a first time stamp to a slave node. The slave node adds a second time stamp and returns the SYNC message to the master node. The master node then adds a third time stamp to the SYNC message. Using the three time stamps, the master node determines if the time clock within the slave node leads or follows the time clock in the master node. The calculation does not depend on the assumption that transmission delays to the slave node are the same as the transmission delays from the node. If the time clocks do not match, the master node sends an INFO message to the slave node informing the slave node of the correct time for clocks within the computer cluster.

Abstract translation: 提供了一种用于计算机集群中的时间同步的系统。 对于本发明的系统，主节点向从节点发送包括第一时间戳的SYNC消息。 从节点添加第二个时间戳，并将SYNC消息返回给主节点。 主节点然后向SYNC消息中添加第三个时间戳。 使用三个时间戳，主节点确定从节点内的时钟是否导通或跟随主节点中的时钟。 计算不取决于对从节点的传输延迟与来自节点的传输延迟相同的假设。 如果时钟不匹配，则主节点向从节点发送INFO消息，通知从节点计算机集群内的时钟的正确时间。