公开(公告)号：US20020004884A1

公开(公告)日：2002-01-10

申请号：US09112082

申请日：1998-07-08

申请人： FUJITSU LIMITED COMPANY, FUJITSU LIMITED

发明人： TERUJI YAMAKAWA ,  KIYOMI IMAMURA

IPC分类号： G06F012/00

CPC分类号： G06F21/80 ,  G11B20/00086 ,  G11B20/0063

摘要： It is provided a data storage device which reads data from and/or writes data to a memory medium, comprising: an acquisition unit for acquiring management information which is recorded by a predetermined form in said memory; and a controller for converting the management information into an another form. The controller rearranges the management information to convert the management information into another form, and also the controller restores the converted management information to the predetermined form according to a relationship between a first identifier recorded on the memory medium and a second identifier recorded in the data storage device. When, for example, the two identifiers match, the acquisition unit can acquire the management information, and the reading and writing of data is enabled. When the two identifiers do not match, restoration of the management information to a predetermined form is not effected, so that the acquisition unit can not acquire the management information and the reading and writing of data is disabled.

摘要翻译： 提供了一种从存储介质读取数据和/或将数据写入存储介质的数据存储装置，包括：获取单元，用于获取以预定形式记录在所述存储器中的管理信息; 以及用于将管理信息转换成另一形式的控制器。 控制器重新排列管理信息以将管理信息转换为另一种形式，并且控制器还根据记录在存储介质上的第一标识符与记录在数据存储器中的第二标识符之间的关系将所转换的管理信息恢复为预定格式 设备。 当例如两个标识符匹配时，获取单元可以获取管理信息，并且能够读取和写入数据。 当两个标识符不匹配时，管理信息恢复到预定的形式不被实现，使得获取单元不能获得管理信息，并且数据的读取和写入被禁止。

公开(公告)号：US5043731A

公开(公告)日：1991-08-27

申请号：US567216

申请日：1990-08-14

申请人： Hirokazu Nishimura

发明人： Hirokazu Nishimura

IPC分类号： H03M1/78

CPC分类号： H03M1/0607 ,  H03M1/785

摘要： A digital-to-analog converter includes a ladder type resistor network having stages equal in number to bits of a digital input signal, each of the stages including a first resistor and a second resistor mutually connected in series via a node. A first switch, which is provided for each of the stages, selectively supplies either an upper limit voltage or a lower limit voltage to a corresponding one of the stages in accordance with a logical value of a corresponding one of the bits of the digital input signal. An analog signal output terminal is coupled to the node of one of the stages which corresponds to a most significant bit of the digital input signal. An analog output signal is output via the analog signal output terminal. An offset level control resistor has a first end connected to the node of one of the stages which corresponds to a least significant bit of the digital input signal and a second end. A second switch, which is coupled to the second end of the offset level control resistor, selectively supplies either the upper limit voltage or the lower limit voltage to the second end of the offset level control resistor.

公开(公告)号：US20080032655A1

公开(公告)日：2008-02-07

申请号：US11869202

申请日：2007-10-09

申请人： Yusuke KAWASAKI ,  Teruhisa NINOMIYA

发明人： Yusuke KAWASAKI ,  Teruhisa NINOMIYA

IPC分类号： H04B1/38 ,  H04B1/18

CPC分类号： G06K7/0008 ,  G06K19/0723 ,  H03D1/04 ,  H04B1/525 ,  H04B1/54 ,  H04L25/062

摘要： A wireless apparatus using the same carrier wave for transmission and reception is configured to store/hold, in a sample-hold circuit SH, a DC component generated by an interference wave, such as a carrier leakage, overlapped on a baseband signal demodulated by a demodulator DEM within a reception circuit of the apparatus, to remove the DC component, and to amplify a desired baseband signal at a high gain in a differential amplification circuit at the next stage.

摘要翻译： 使用相同载波进行发送和接收的无线装置被配置为在采样保持电路SH中存储/保持由诸如载波泄漏的干扰波产生的DC分量，重叠在由 在装置的接收电路内的解调器DEM，以去除DC分量，并在下一级的差分放大电路中以高增益放大期望的基带信号。

公开(公告)号：US4488268A

公开(公告)日：1984-12-11

申请号：US425649

申请日：1982-09-28

申请人： Kazuhiro Toyoda

发明人： Kazuhiro Toyoda

IPC分类号： G11C11/415 ,  G11C13/00

CPC分类号： G11C11/415

摘要： A semiconductor memory includes memory cells and a discharge current source for quickly discharging electric charges, in the form of a discharge current, stored along the word lines. Each of the memory cells is comprised of a load transistor pair and a multi-emitter type detection transistor pair. The discharge current source controls the discharge current by means of a bias circuit formed in the discharge current source. The bias circuit control the value of the discharge current in accordance with the value of an inverse .beta. (current amplification factor) defined by the detection transistors.

摘要翻译： 半导体存储器包括存储单元和用于以沿着字线存储的放电电流形式的电荷快速放电的放电电流源。 每个存储单元由负载晶体管对和多发射体型检测晶体管对构成。 放电电流源通过形成在放电电流源中的偏置电路来控制放电电流。 偏置电路根据由检测晶体管限定的反β（电流放大因子）的值来控制放电电流的值。

公开(公告)号：US20210288682A1

公开(公告)日：2021-09-16

申请号：US17197295

申请日：2021-03-10

申请人： FUJITSU LIMITED ,  FUJITSU LIMITED

发明人： Tomoya OTA ,  Hiroyoshi ISHIKAWA ,  Alexander Nikolaevich LOZHKIN ,  Toru MANIWA

IPC分类号： H04B1/04 ,  H03F3/24 ,  H04L27/36 ,  H03F1/32

摘要： A wireless communication apparatus includes: a processor that performs distortion compensation on a complex number transmission signal by using a distortion compensation coefficient; a power amplifier that amplifies the transmission signal subjected to distortion compensation by the processor; and a feedback path that feeds back a signal output from the power amplifier to supply a real number feedback signal to the processor. The processor executes a process including: estimating a complex number feedback signal by performing linear computation on the complex number transmission signal and the real number feedback signal; and updating the distortion compensation coefficient by using the estimated complex number feedback signal.

公开(公告)号：US20080226136A1

公开(公告)日：2008-09-18

申请号：US11854884

申请日：2007-09-13

申请人： Kazuo TAKAKU ,  Yasuhiko MITA ,  Naoko SUZUKI ,  Shinya IWASAKI ,  Masayuki YANO

发明人： Kazuo TAKAKU ,  Yasuhiko MITA ,  Naoko SUZUKI ,  Shinya IWASAKI ,  Masayuki YANO

IPC分类号： G06K9/00

CPC分类号： G07C9/00158 ,  G06K9/00375 ,  G06K9/00912 ,  G06K2009/00932 ,  G07C9/00166 ,  G07C2209/02

摘要： A biometrics authentication device identifies characteristics of the body from captured images of the body and performs individual authentication. The device guides a user, at the time of verification, to the image capture state at the time of registration of biometrics characteristic data. At the time of registration of biometrics characteristic data, body image capture state data is extracted from an image captured by an image capture unit and is registered in a storage unit, and at the time of verification the registered image capture state data is read from the storage unit and is compared with image capture state data extracted at the time of verification, and guidance of the body is provided. Alternatively, an outline of the body at the time of registration, taken from image capture state data at the time of registration, is displayed.

摘要翻译： 生物特征认证装置从身体的捕获图像识别身体的特征并执行个体认证。 该装置在验证时引导用户注册生物特征数据时的图像捕获状态。 在生物识别特征数据的登记时，从图像拍摄单元拍摄的图像中提取身体图像拍摄状态数据，并将其登记在存储单元中，并且在验证时，登记图像捕获状态数据从 与验证时提取的图像捕获状态数据进行比较，并提供身体的引导。 或者，显示从注册时的图像拍摄状态数据取得的注册时的身体的轮廓。

公开(公告)号：US20240362096A1

公开(公告)日：2024-10-31

申请号：US18632516

申请日：2024-04-11

申请人： Fujitsu Limited

发明人： Satoshi KAZAMA ,  Kazuhiro SUZUKI ,  Hiroshi ENDO

IPC分类号： G06F11/00

CPC分类号： G06F11/006

摘要： A memory stores management information where identification information of each of a plurality of devices used by an information processing apparatus, first positional information, and second positional information are associated with one another. The first positional information indicates a position of a device storage storing the plurality of devices. The second positional information indicates a storage position of each of the plurality of devices in the device storage. A processor receives failed device information including identification information of a failed device among the plurality of devices from the information processing apparatus. The processor identifies the position of the device storage storing the failed device and the storage position of the failed device in the device storage from the identification information of the failed device included in the failed device information on the basis of management information.

公开(公告)号：US20240357448A1

公开(公告)日：2024-10-24

申请号：US18757796

申请日：2024-06-28

申请人： FUJITSU LIMITED

发明人： Guorong LI ,  Meiyi JIA ,  Xin WANG

IPC分类号： H04W36/00 ,  H04W36/30 ,  H04W88/04

CPC分类号： H04W36/033 ,  H04W36/30 ,  H04W88/04

摘要： An apparatus, configured in a first terminal equipment, wherein the apparatus includes: communicator configured to communicate a second terminal equipment via a relay device; and processor circuitry configured to trigger a selection process of the relay device or a reselection process of the relay device in a first situation.

公开(公告)号：US12127156B2

公开(公告)日：2024-10-22

申请号：US16280130

申请日：2019-02-20

申请人： FUJITSU LIMITED

发明人： Meiyi Jia ,  Yulong Shi ,  Lianhai Wu ,  Hua Zhou

IPC分类号： H04W64/00 ,  H04W4/029 ,  H04W48/12 ,  H04W52/02 ,  H04W60/04 ,  H04W76/11 ,  H04W76/40

CPC分类号： H04W64/003 ,  H04W4/029 ,  H04W64/00 ,  H04W76/11 ,  H04W76/40 ,  H04W48/12 ,  H04W52/0229 ,  H04W60/04

摘要： An area identifying apparatus and method and a communication system. The area identifying method includes: receiving, by a UE, area identification information used for identifying an area transmitted by a base station; comparing the received area identification information with area identification information currently stored in the UE; and determining whether an area where the UE is located is changed according to a result of comparison. Hence, whether the area where the UE is located is changed or which area the UE is located may be efficiently identified.

公开(公告)号：US12126386B2

公开(公告)日：2024-10-22

申请号：US17953375

申请日：2022-09-27

申请人： Fujitsu Limited

发明人： Shinsuke Tanaka ,  Tomoyuki Akiyama

IPC分类号： H04B10/50 ,  H04B10/548

CPC分类号： H04B10/548 ,  H04B10/501

摘要： Optical transmitter includes: signal processing circuit, optical modulator, optical filter, and delay circuit. The signal processing circuit generates N drive signals for generating a modulated optical signal. Symbol rate of the modulated optical signal is fs and each symbol of the modulated optical signal transmits N bits. The optical modulator includes Mach-Zehnder interferometer and N phase-shift segments each of which shifts a phase of light propagating through an optical path of the Mach-Zehnder interferometer according to the N drive signals. The optical filter removes, from output light of the optical modulator, a frequency component in a range of ±fs/2 with respect to a center frequency of the modulated optical signal, and extracts at least a part of other frequency components. The delay circuit controls timings of the N drive signals so as to reduce optical power of the frequency component extracted by the optical filter.