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    Storage drive dependent track removal in a cache for storage
    2.
    发明授权
    Storage drive dependent track removal in a cache for storage 有权

    公开(公告)号：US11620219B2

    公开(公告)日：2023-04-04

    申请号：US16953046

    申请日：2020-11-19

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Kevin J. Ash ,  Matthew G. Borlick ,  Lokesh M. Gupta ,  Trung N. Nguyen

    IPC: G06F12/0804 ,  G06F12/121 ,  G06F12/0868

    Abstract: In one embodiment, storage drive dependent track removal processing logic performs destage tasks for tracks cached in a cache as a function of whether the storage drive is classified as a fast class or as slow class of storage drives, for example. In one embodiment, a destage task configured for a slow class storage drive, transfers an entry for a track selected for destaging from a main cache list to a wait cache list to await destaging to the slow class drive. A destage task configured for a fast class storage drive allows the cache list entry for the selected track to remain on the main cache list while the selected track is being destaged to the fast class storage drive, thereby bypassing the transfer of the entry to a wait cache list. Other features and aspects may be realized, depending upon the particular application.

    DYNAMICALLY ADJUSTING PARTITIONED SCM CACHE MEMORY TO MAXIMIZE PERFORMANCE
    6.
    发明申请
    DYNAMICALLY ADJUSTING PARTITIONED SCM CACHE MEMORY TO MAXIMIZE PERFORMANCE 有权

    公开(公告)号：US20220188235A1

    公开(公告)日：2022-06-16

    申请号：US17119470

    申请日：2020-12-11

    Applicant: International Business Machines Corporation

    Inventor： Lokesh M. Gupta ,  Kevin J. Ash ,  Kyler A. Anderson ,  Matthew G. Borlick

    IPC: G06F12/0846 ,  G06F3/06

    Abstract: A method for dynamically adjusting cache memory partition sizes within a storage system includes computing a read hit ratio for data accessed in each cache partition and an average read hit ratio for all the cache partitions over a time interval. The cache memory includes a higher performance portion (DRAM) and lower performance portion (SCM). The method increases or decreases the partition size for each cache partition by comparing the read hit ratio for the partition to the average read hit ratio for all the partitions. Each cache partition includes maximum and minimum partition sizes, and read hit and read access counters. The SCM portion of the cache memory includes cache partitions reserved for storing data of a specific type, or data used for a specific purpose or with a specific software application. A corresponding storage controller and computer program product are also disclosed.

    Using real segments and alternate segments in non-volatile storage
    7.
    发明授权
    Using real segments and alternate segments in non-volatile storage 有权

    公开(公告)号：US11314659B2

    公开(公告)日：2022-04-26

    申请号：US15696037

    申请日：2017-09-05

    Applicant: International Business Machines Corporation

    Inventor： Kyler A. Anderson ,  Kevin J. Ash ,  Lokesh M. Gupta ,  Matthew J. Kalos

    IPC: G06F12/1045 ,  G06F12/0868 ,  G06F3/06 ,  G06F12/02 ,  G06F13/24 ,  G06F13/40 ,  G06F13/42

    Abstract: Provided are techniques for using real segments and alternate segments in Non-Volatile Storage (NVS). One or more write requests for a track are executed by alternating between storing data in one or more sectors of real segments and one or more sectors of alternate segments for each of the write requests, while setting indicators in a real sector structure and an alternate sector structure. In response to determining that the one or more write requests for the track have completed, the data stored in the one or more sectors of the real segments and in the one or more sectors of the alternate segments are merged to form newly written data. In response to determining that a hardened, previously written data of a track does exist in Non-Volatile Storage (NVS), the newly written data is merged with the hardened, previously written data in the NVS. The merged data is committed.

    Fixing anomalies in a preserved data structure used to generate a temporary data structure during system initialization
    9.
    发明授权
    Fixing anomalies in a preserved data structure used to generate a temporary data structure during system initialization 有权

    公开(公告)号：US11294886B2

    公开(公告)日：2022-04-05

    申请号：US16788301

    申请日：2020-02-11

    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

    Inventor： Matthew G. Borlick ,  Lokesh M. Gupta ,  Clint A. Hardy

    IPC: G06F16/23 ,  G06F3/06 ,  G06F11/14 ,  G06F11/07

    Abstract: Provided are a computer program product, system, and method for fixing anomalies in a preserved data structure used to generate a temporary data structure during system initialization. A preserved data structure in persistent storage is used to build a temporary data structure in a memory of the computing system during initialization of the computing system. The temporary data structure represents computational resources in the computing system and is rebuilt from the preserved data structure during the initialization. The preserved data structure and the temporary data structure are processed to determine whether the preserved data structure includes at least one anomaly that would result in rebuilding the temporary data structure with an error. Information on the preserved data structure and the temporary data structure having the anomaly are processed to determine modifications to correct the preserved data structure. The determined modifications are processed to correct the preserved data structure.

    Dispatching tasks on processors based on memory access efficiency
    10.
    发明授权
    Dispatching tasks on processors based on memory access efficiency 有权

    公开(公告)号：US11281502B2

    公开(公告)日：2022-03-22

    申请号：US16798339

    申请日：2020-02-22

    Applicant: International Business Machines Corporation

    Inventor： Lokesh M. Gupta ,  Matthew J. Kalos ,  Kevin J. Ash ,  Trung N. Nguyen

    IPC: G06F9/46 ,  G06F9/50 ,  G06F9/48

    Abstract: A method for dispatching tasks on processor cores based on memory access efficiency is disclosed. The method identifies a task and a memory area to be accessed by the task. The method may use one or more of a compiler, code knowledge, and run-time statistics to identify the memory area that is accessed by the task. The method identifies multiple processor cores that are candidates to execute the task and identifies a particular processor core from the multiple processor cores that provides most efficient access to the memory area. The method dispatches the task to execute on the particular processor core that is deemed most efficient. A corresponding system and computer program product are also disclosed.

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