公开(公告)号：US20090302423A1

公开(公告)日：2009-12-10

申请号：US12457037

申请日：2009-05-29

Applicant: Yukio Takahashi ,  Kousuke Yoshida

Inventor： Yukio Takahashi ,  Kousuke Yoshida

IPC: H01L29/73

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer.

Abstract translation: 静电放电保护电路具有双极晶体管，其包括与第一电源连接并用作基极的第一导电类型的第一扩散层; 与第二电源连接并用作集电器的第二导电类型的第二扩散层; 以及与输入/输出焊盘连接并用作发射极的第二导电类型的第三扩散层。 与第一扩散层相对的第三扩散层的第一区域的面积大于与第一扩散层相反的第二扩散层的第二区域的面积。

公开(公告)号：US08536680B2

公开(公告)日：2013-09-17

申请号：US12457037

申请日：2009-05-29

Applicant: Yukio Takahashi ,  Kousuke Yoshida

Inventor： Yukio Takahashi ,  Kousuke Yoshida

IPC: H01L27/102

CPC classification number: H01L27/0259

Abstract: An electrostatic discharge protection circuit has a bipolar transistor which includes a first diffusion layer of a first conductive type connected with a first power supply and functioning as a base; a second diffusion layer of a second conductive type connected with a second power supply and functioning as a collector; and a third diffusion layer of the second conductive type connected with an input/output pad and functioning as an emitter. An area of a first region of the third diffusion layer which is opposite to the first diffusion layer is larger than an area of a second region of the second diffusion layer which is opposite to the first diffusion layer.

公开(公告)号：US5723886A

公开(公告)日：1998-03-03

申请号：US307487

申请日：1994-09-16

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L27/01 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L21/28123 ,  H01L29/0638

Abstract: The invention provides an n-channel MOS field effect transistor with an improved anti-radioactivity. Such transistor includes a p-type silicon substrate. An isolation oxide film is selectively formed on a surface of the p-type silicon substrate. Source and drain diffusion layers of n+-type are formed on first opposite sides of a channel region in the p-type silicon substrate. A gate made of polycrystalline silicon is formed over the channel region through a gate oxide film. Leak guard diffusion layers of p-type are formed on second opposite sides of the channel region in the p-type silicon substrate. The p-type leak guard diffusion layer has a junction surface to the isolation oxide film. The junction surface of the p-type leak guard diffusion layer and the isolation oxide film exists up to a level which is deeper than a depth of the n+-type source and drain diffusion layers.

Abstract translation: 本发明提供具有改进的抗放射性的n沟道MOS场效应晶体管。 这种晶体管包括p型硅衬底。 在p型硅衬底的表面上选择性地形成隔离氧化膜。 在p型硅衬底的沟道区的第一相对侧上形成n +型源极和漏极扩散层。 通过栅极氧化膜在沟道区域上形成由多晶硅制成的栅极。 在p型硅衬底的沟道区的第二相对侧上形成有p型漏泄保护层。 p型防漏扩散层具有与隔离氧化膜的接合面。 p型防漏扩散层和隔离氧化膜的结表面存在的深度比n +型源极和漏极扩散层的深度更深。

公开(公告)号：US5747354A

公开(公告)日：1998-05-05

申请号：US644307

申请日：1996-05-10

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H01L21/76 ,  H01L21/265 ,  H01L21/28 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L21/28123 ,  H01L29/0638

Abstract: The invention provides an n-channel MOS field effect transistor with an anti-radioactivity. The transistor includes leak guard boron diffusion layers, each of which has a junction surface to an isolation oxide film. The junction surface exists up to a deeper level than a predetermined depth corresponding to a junction surface of n-type source and drain diffusion layers and a p-type silicon substrate. Such leak guard boron diffusion layer is formed by ion-implantation of boron through a gate oxide film, after a formation of the gate oxide film. Such leak guard boron diffusion layers have a higher impurity concentration. The existence of the leak guard boron diffusion layers suppresses a leak to be generated by radiation damages of silicon oxide film such as the gate oxide film and the isolation oxide film.

Abstract translation: 本发明提供具有抗放射性的n沟道MOS场效应晶体管。 晶体管包括泄漏保护硼扩散层，每个漏极具有与隔离氧化膜的接合面。 接合表面存在的深度比对应于n型源极和漏极扩散层的结表面和p型硅衬底的预定深度更深。 在形成栅极氧化膜之后，通过栅极氧化膜离子注入硼而形成这种防漏硼扩散层。 这种泄漏保护硼扩散层具有较高的杂质浓度。 泄漏保护硼扩散层的存在抑制了由诸如栅极氧化膜和隔离氧化物膜的氧化硅膜的辐射损伤而产生的泄漏。

公开(公告)号：US08445801B2

公开(公告)日：2013-05-21

申请号：US12016719

申请日：2008-01-18

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H01H3/12

CPC classification number: H01H13/04 ,  H01H13/14

Abstract: A switch comprises a room light case, a switch knob arranged inside an aperture portion of the room light case, guide grooves provided on an inner circumferential face of the aperture portion of the room light case, and guide ribs provided on an outer circumferential face of the switch knob. The switch knob moves for a switch stroke part in a depth direction of the aperture portion, from a waiting position to a pressed-down position by a pressing down operation. The guide grooves are provided in a range deeper than a depth size of the switch stroke from an opening edge located on the switch case surface side of the aperture portion.

Abstract translation: 开关包括房间灯箱，设置在房间灯箱的开口部内的开关钮，设置在室内灯罩的开口部的内周面上的导向槽，以及设置在室内灯壳的外周面的导向肋 开关旋钮。 开关旋钮沿着开口部的深度方向移动开关笔划部分，通过按压操作从等待位置移动到按下位置。 引导槽从位于开口部的开关壳体表面侧的开口边缘设置在比开关行程的深度尺寸更深的范围内。

公开(公告)号：US20100244129A1

公开(公告)日：2010-09-30

申请号：US12659450

申请日：2010-03-09

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7836 ,  H01L29/42368 ,  H01L29/66568

Abstract: Second-conductivity-type high dose impurity layers are formed in a device forming region, and function as the source and drain; a second-conductivity-type low dose impurity layer is provided around each of the second-conductivity-type high dose impurity layers so as to expand each second-conductivity-type high dose impurity layer in the depth-wise direction and in the direction of channel length, at least a part of the second-conductivity-type low dose impurity layer is positioned below the gate electrode, and the gate insulting film; and the gate insulating film has, at a portion thereof positioned above the second-conductivity-type low dose impurity layer, a sloped portion which continuously increases in the thickness from the center towards a side face of the gate electrode, without causing an inflection point.

Abstract translation: 第二导电型高剂量杂质层形成在器件形成区域中，起到源极和漏极的作用; 在每个第二导电型高剂量杂质层周围设置第二导电型低剂量杂质层，以使第二导电型高剂量杂质层沿深度方向和 沟道长度，第二导电型低剂量杂质层的至少一部分位于栅电极下方，栅极绝缘膜; 并且栅极绝缘膜在其位于第二导电型低剂量杂质层之上的部分处具有从栅极的中心朝向侧面的厚度连续增加的倾斜部分，而不产生拐点 。

公开(公告)号：US20090242984A1

公开(公告)日：2009-10-01

申请号：US12379512

申请日：2009-02-24

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7835 ,  H01L29/1087

Abstract: Aimed at providing a semiconductor device capable preventing transistor characteristics from departing from design characteristics, the semiconductor device of the present invention has a gate insulating film and a gate electrode positioned over a channel forming region; two second-conductivity-type, high-concentration impurity diffused layers which function as the source and drain of a transistor; two second-conductivity-type, low-concentration impurity diffused layers having a concentration lower than that of the second-conductivity-type, high-concentration impurity diffused layers, provided respectively around the second-conductivity-type, high-concentration impurity diffused layers, so as to expand the second-conductivity-type, high-concentration impurity diffused layers in the depth-wise direction and the channel-length-wise direction; and a first-conductivity-type buried layer having a concentration higher than that of the semiconductor layer, positioned below the second-conductivity-type, low-concentration impurity diffused layers, and extended from an area below the channel forming region via an area below the device isolation film towards the outer periphery of the device isolation film.

Abstract translation: 为了提供能够防止晶体管特性脱离设计特性的半导体器件，本发明的半导体器件具有栅极绝缘膜和位于沟道形成区域上方的栅电极; 用作晶体管的源极和漏极的两个第二导电型，高浓度杂质扩散层; 分别设置在第二导电型高浓度杂质扩散层周围的具有低于第二导电型高浓度杂质扩散层的浓度的二次导电型低浓度杂质扩散层 以便在深度方向和通道长度方向上扩展第二导电型，高浓度杂质扩散层; 以及位于第二导电型低浓度杂质扩散层下方的浓度高于半导体层的第一导电型掩埋层，并且从沟道形成区域下方的区域延伸经由下面的区域 器件隔离膜朝向器件隔离膜的外周。

公开(公告)号：US06476641B2

公开(公告)日：2002-11-05

申请号：US09898979

申请日：2001-07-03

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H03K19094

CPC classification number: G11C11/412

Abstract: A low power consuming circuit is provided which is capable of reducing power consumption by using a Vt (threshold voltage) characteristic of a MIS (Metal Insulator Semiconductor) transistor for generating a source voltage. N-channel transistors making up an inverter is configured by being stacked vertically. An N-channel transistor source voltage control circuit controls voltages so that a gate voltage of an N-channel transistor source voltage bias transistor existing in a lower state is transferred to a drain voltage terminal of the N-channel transistor source voltage bias transistor or to a supply voltage terminal.

Abstract translation: 提供了一种能够通过使用用于产生源极电压的MIS（金属绝缘体半导体）晶体管的Vt（阈值电压）特性来降低功耗的低功耗电路。 构成逆变器的N沟道晶体管通过垂直堆叠而构成。 N沟道晶体管源极电压控制电路控制电压，使得存在于较低状态的N沟道晶体管源极电压偏置晶体管的栅极电压被传送到N沟道晶体管源极电压偏置晶体管的漏极电压端子，或者 电源电压端子。

公开(公告)号：US5990731A

公开(公告)日：1999-11-23

申请号：US17862

申请日：1998-02-03

Applicant: Kousuke Yoshida

Inventor： Kousuke Yoshida

IPC: H01L27/06 ,  H01L27/02 ,  G05F1/10

CPC classification number: H01L27/0251

Abstract: Input/output circuitry for electrically protecting an internal element includes an input/output terminal connected to the internal element, a pair of first and second power terminals applied with a bias voltage, a series connection of a diode and a bipolar transistor between the pair of first and second power terminals so that an intermediate point between the diode and the bipolar transistor is connected to the input terminal, and a parasitic resistance connected between a base of the bipolar transistor and the diode so that the diode is connected between the parasitic resistance and an emitter of the bipolar transistor. An electrostatic pulse applied to the input/output terminal is clamped by the series connection of the diode and the bipolar transistor to protect the internal element from an electrostatic pulse applied to the input/output terminal.

Abstract translation: 用于电保护内部元件的输入/输出电路包括连接到内部元件的输入/输出端子，施加偏置电压的一对第一和第二电源端子，二极管和双极晶体管的串联连接在一对 第一和第二电源端子，使得二极管和双极晶体管之间的中间点连接到输入端，以及连接在双极晶体管的基极和二极管之间的寄生电阻，使得二极管连接在寄生电阻和 双极晶体管的发射极。 施加到输入/输出端子的静电脉冲被二极管和双极晶体管的串联连接钳位，以保护内部元件免受施加到输入/输出端子的静电脉冲。

公开(公告)号：US5160708A

公开(公告)日：1992-11-03

申请号：US755642

申请日：1991-09-06

Applicant: Kenzaburo Kodama ,  Kenji Kamei ,  Kousuke Yoshida ,  Katsuya Ishikawa ,  Yukio Kubo ,  Yoshiaki Takatani

Inventor： Kenzaburo Kodama ,  Kenji Kamei ,  Kousuke Yoshida ,  Katsuya Ishikawa ,  Yukio Kubo ,  Yoshiaki Takatani

IPC: B01D46/34 ,  B01D53/52 ,  C10K1/20

CPC classification number: C10K1/20 ,  B01D46/34 ,  B01D53/52

Abstract: The invention relates to a dry type simultaneous desulfurization and dedusting method in forming moving beds with a granulate desulfurizing and dedusting agent containing as the principle composition 5-95 weight % of iron oxide and 95-5 weight % of metallic iron, and contacting these moving beds with the gas containing hydrogen sulfide and dust, thereby simultaneously desulfurizing and dedusting the gas.

Abstract translation: 本发明涉及一种干燥型同时脱硫除尘方法，用颗粒脱硫除尘剂形成移动床，其主要组成为氧化铁的5-95重量％和金属铁的95-5重量％，并将这些移动 床上含有硫化氢和粉尘的气体，从而同时对气体进行脱硫除尘。