公开(公告)号：US08823691B2

公开(公告)日：2014-09-02

申请号：US13348673

申请日：2012-01-12

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0281 ,  G09G2320/0219

摘要： A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.

摘要翻译： 显示装置包括：多个像素组，每个像素组包括像素电路; 多个扫描线，其各自连接到包括在任何一个像素组中的像素电路; 时钟信号供给电路，其提供包括脉冲信号的时钟信号; 移位寄存器电路，其以预定顺序选择性地将扫描线传送到扫描线; 以及连接到像素电路并且将数据信号提供给要扫描的像素组中包括的像素电路的数据信号线。 提供给一些扫描线的脉冲信号的周期长于提供给其它扫描线的脉冲信号的周期，或者数据信号由包括在像素电路中的晶体管传输。

公开(公告)号：US08542179B2

公开(公告)日：2013-09-24

申请号：US12977941

申请日：2010-12-23

申请人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

发明人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

摘要： A gate signal line driving circuit and a display device includes first and second low voltage application switching elements that supply a low voltage to gate signal lines, a holding capacitor that is connected to a reset target node and supplies an ON signal towards the first and second low voltage application switching elements in a signal low period, first and third control switching elements the one ends of which are connected to the switch input of the first or second low voltage application switching element, and second and fourth control switching elements which each are provided between the switch input of the first or second low voltage application switching element and one end of the holding capacitor. In a startup period, a high voltage is supplied to the holding capacitor through the first to fourth control switching elements.

摘要翻译： 栅极信号线驱动电路和显示装置包括向栅极信号线提供低电压的第一和第二低电压施加开关元件，连接到复位目标节点的保持电容器，并向第一和第二 信号低周期中的低电压应用开关元件，其一端连接到第一或第二低电压应用开关元件的开关输入的第一和第三控制开关元件，以及各自提供的第二和第四控制开关元件 在第一或第二低电压施加开关元件的开关输入和保持电容器的一端之间。 在启动期间，通过第一至第四控制开关元件向保持电容器提供高电压。

公开(公告)号：US08339390B2

公开(公告)日：2012-12-25

申请号：US12625683

申请日：2009-11-25

申请人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

发明人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G2330/02 ,  G09G2330/021 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

摘要： Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.

摘要翻译： 提供了即使在电流消耗变化的显示面板上也能够提高功率效率的电源电路和显示装置。 电源电路使用升压斩波电路来提升输出电压。 频率控制电路根据电源电路的负载改变控制斩波电路的开关的时钟信号的频率。 频率控制电路基于垂直同步信号和水平同步信号，在低负载下将显示装置的操作划分为高负载和垂直回扫周期的显示有效期间。 频率控制电路将高负载时段的时钟信号的频率设定为比低负载期间的频率高。

公开(公告)号：US20110157112A1

公开(公告)日：2011-06-30

申请号：US12977941

申请日：2010-12-23

申请人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

发明人： Takeshi Shibata ,  Yoshihiro Kotani ,  Takahiro Ochiai ,  Mitsuru Goto

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G09G2300/0426 ,  G11C19/184

摘要： A gate signal line driving circuit and a display device includes first and second low voltage application switching elements that supply a low voltage to gate signal lines, a holding capacitor that is connected to a reset target node and supplies an ON signal towards the first and second low voltage application switching elements in a signal low period, first and third control switching elements the one ends of which are connected to the switch input of the first or second low voltage application switching element, and second and fourth control switching elements which each are provided between the switch input of the first or second low voltage application switching element and one end of the holding capacitor. In a startup period, a high voltage is supplied to the holding capacitor through the first to fourth control switching elements.

摘要翻译： 栅极信号线驱动电路和显示装置包括向栅极信号线提供低电压的第一和第二低电压施加开关元件，连接到复位目标节点的保持电容器，并向第一和第二 信号低周期中的低电压应用开关元件，其一端连接到第一或第二低电压应用开关元件的开关输入的第一和第三控制开关元件，以及各自提供的第二和第四控制开关元件 在第一或第二低电压施加开关元件的开关输入和保持电容器的一端之间。 在启动期间，通过第一至第四控制开关元件向保持电容器提供高电压。

公开(公告)号：US20100128022A1

公开(公告)日：2010-05-27

申请号：US12625683

申请日：2009-11-25

申请人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

发明人： Naoki Takada ,  Naruhiko Kasai ,  Takuya Eriguchi ,  Yuki Okada ,  Mitsuru Goto ,  Yoshihiro Kotani

IPC分类号： G06F3/038

CPC分类号： G09G3/3696 ,  G09G2330/02 ,  G09G2330/021 ,  H02M3/07 ,  H02M3/156 ,  H02M2001/0032 ,  Y02B70/16

摘要： Provided are a power supply circuit and a display device which are capable of enhancing power efficiency even when applied to a display panel whose current consumption varies. The power supply circuit boosts and outputs an input voltage using a booster chopper circuit. A frequency control circuit changes a frequency of a clock signal, which controls a switch of the chopper circuit, in accordance with a load of the power supply circuit. The frequency control circuit divides an operation of the display device into a display effective period at a high load and a vertical retrace period at a low load, based on a vertical synchronizing signal and a horizontal synchronizing signal. The frequency control circuit sets the frequency of the clock signal in a high-load period to be higher than that in a low-load period.

摘要翻译： 提供了即使在电流消耗变化的显示面板上也能够提高功率效率的电源电路和显示装置。 电源电路使用升压斩波电路来提升输出电压。 频率控制电路根据电源电路的负载改变控制斩波电路的开关的时钟信号的频率。 频率控制电路基于垂直同步信号和水平同步信号，在低负载下将显示装置的操作划分为高负载和垂直回扫周期的显示有效期间。 频率控制电路将高负载时段的时钟信号的频率设定为比低负载期间的频率高。

公开(公告)号：US20080084380A1

公开(公告)日：2008-04-10

申请号：US11865747

申请日：2007-10-02

申请人： Yoshihiro Kotani ,  Yoshinori Aoki ,  Mitsuru Goto

发明人： Yoshihiro Kotani ,  Yoshinori Aoki ,  Mitsuru Goto

IPC分类号： G09G3/12

CPC分类号： G09G3/3696

摘要： A display device includes a display panel and a driving circuit for driving each pixel of the display panel, in which a VCCIO voltage and a VCC voltage equal to or larger than the VCCIO voltage (VCCIO≦VCC) is inputted to the driving circuit. The driving circuit has a first level conversion circuit for converting a signal voltage level from a VCCIO voltage level to a VCC voltage level, and a level sense circuit for detecting a state in which the VCCIO voltage is not inputted. When the state in which the VCCIO voltage is not inputted is detected in the level sense circuit, operation of the first level conversion circuit is stopped. The driving circuit has a Vdd control signal for controlling operation of a Vdd voltage generation circuit, and the level sense circuit is a NAND circuit having the VCC voltage as a power supply voltage and having the VCCIO voltage and the Vdd control signal as inputs.

摘要翻译： 显示装置包括显示面板和用于驱动显示面板的每个像素的驱动电路，其中VCCIO电压和等于或大于VCCIO电压（VCCIO <= VCC）的VCC电压被输入到驱动电路。 驱动电路具有用于将信号电压电平从VCCIO电压电平转换为VCC电压电平的第一电平转换电路和用于检测VCCIO电压未被输入的状态的电平检测电路。 当在电平检测电路中检测到没有输入VCCIO电压的状态时，停止第一电平转换电路的操作。 驱动电路具有用于控制Vdd电压产生电路的操作的Vdd控制信号，电平检测电路是具有VCC电压作为电源电压并具有VCCIO电压和Vdd控制信号作为输入的NAND电路。

公开(公告)号：US09336899B2

公开(公告)日：2016-05-10

申请号：US13334280

申请日：2011-12-22

申请人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Takahiro Ochiai ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G09G3/34 ,  G11C19/28 ,  G09G3/36

CPC分类号： G11C19/287 ,  G09G3/3677 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021

摘要： A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.

摘要翻译： 提供能够在两个方向上执行稳定的移位操作的双向移位寄存器和使用其的图像显示装置。 在正向移位操作中，当参考点N1处于H电平时，作为双向移位寄存器的后级的第（n + 4）单位寄存器电路与时钟脉冲V（n + 4）同步地输出脉冲G（n + 4）输入到第（n + 4）个单元寄存器电路。 不仅在反向开始时产生反向触发信号VSTB，而且例如在紧接在G（n + 4）之后的单相时钟的周期（时刻t4〜t5）中垂直输出 向前移位的消隐间隔。 反向触发信号VSTB被输入到在第（n + 4）个单位寄存器电路的参考点N1设置为H电平的晶体管的栅极上，在反向启动时为止。

公开(公告)号：US20120182279A1

公开(公告)日：2012-07-19

申请号：US13348673

申请日：2012-01-12

申请人： Takahiro OCHIAI ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Takahiro OCHIAI ,  Mitsuru Goto ,  Hiroyuki Higashijima ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G09G5/00

CPC分类号： G09G3/3648 ,  G09G3/3614 ,  G09G3/3677 ,  G09G2310/0281 ,  G09G2320/0219

摘要： A display device includes: plural pixel groups each including pixel circuits; plural scanning lines that are each connected to the pixel circuits included in any one of the pixel groups; a clock signal supply circuit that supplies a clock signal including a pulse signal; a shift register circuit that selectively transmits the pulse signal to the scanning lines in a predetermined order; and data signal lines that are connected to the pixel circuits and that supply a data signal to the pixel circuits included in the pixel group to be scanned. The period of the pulse signal supplied to some of the scanning lines is longer than the period of the pulse signal supplied to the other scanning lines, or the data signal is transmitted by the transistors included in the pixel circuits.

摘要翻译： 显示装置包括：多个像素组，每个像素组包括像素电路; 多个扫描线，其各自连接到包括在任何一个像素组中的像素电路; 时钟信号供给电路，其提供包括脉冲信号的时钟信号; 移位寄存器电路，其以预定顺序选择性地将扫描线传送到扫描线; 以及连接到像素电路并且将数据信号提供给要扫描的像素组中包括的像素电路的数据信号线。 提供给一些扫描线的脉冲信号的周期长于提供给其它扫描线的脉冲信号的周期，或者数据信号由包括在像素电路中的晶体管传输。

公开(公告)号：US08638284B2

公开(公告)日：2014-01-28

申请号：US12761423

申请日：2010-04-16

申请人： Yoshihiro Kotani ,  Mitsuru Goto

发明人： Yoshihiro Kotani ,  Mitsuru Goto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G11C19/184 ,  G11C19/28

摘要： A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.

摘要翻译： 提供了能够长时间抑制归因于元件的元素的劣化的栅极信号线驱动电路和显示装置，并且可以实现元件的使用寿命的延长。 对于长时间施加高电压的元件，多个元件并联连接，并且多个元件中的至少一些元件由开关元件驱动。

公开(公告)号：US20100265243A1

公开(公告)日：2010-10-21

申请号：US12761423

申请日：2010-04-16

申请人： Yoshihiro KOTANI ,  Mitsuru Goto

发明人： Yoshihiro KOTANI ,  Mitsuru Goto

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G11C19/184 ,  G11C19/28

摘要： A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.

摘要翻译： 提供了能够长时间抑制归因于元件的元素的劣化的栅极信号线驱动电路和显示装置，并且可以实现元件的使用寿命的延长。 对于长时间施加高电压的元件，多个元件并联连接，并且多个元件中的至少一些元件由开关元件驱动。