公开(公告)号：US08531377B2

公开(公告)日：2013-09-10

申请号：US12292447

申请日：2008-11-19

申请人： Yoshihiro Kotani ,  Kenichi Akiyama

发明人： Yoshihiro Kotani ,  Kenichi Akiyama

IPC分类号： G09G3/36

CPC分类号： G09G3/3696 ,  G09G3/3688 ,  G09G2310/0218

摘要： A liquid crystal display device used in miniaturized portable equipment includes a distribution circuit to cope with a high-definition multi-grayscale display. A distribution circuit distributes an output of a drive circuit to a plurality of video signal lines within one scanning period, the distribution circuit being divided into a plurality of distribution circuits, and control signals being supplied to each distribution circuit from both end portions of each distribution circuit. When an output part of the drive circuit is configured such that a high withstand-voltage output amplifier and a low withstand-voltage output amplifier are alternately connected with the distribution circuit, a master function and a slave function are imparted to the drive circuit so as to allow the drive circuit to cope with odd-numbered outputs.

摘要翻译： 用于小型化便携式设备的液晶显示装置包括用于应对高分辨率多灰阶显示的分配电路。 分配电路在一个扫描周期内将驱动电路的输出分配给多个视频信号线，分配电路被分成多个分配电路，并且控制信号从每个分配的两个端部提供给每个分配电路 电路。 当驱动电路的输出部分被配置为使得高耐压输出放大器和低耐压输出放大器与分配电路交替连接时，将主功能和从功能赋予驱动电路，以便 以允许驱动电路处理奇数输出。

公开(公告)号：US08477131B2

公开(公告)日：2013-07-02

申请号：US12825596

申请日：2010-06-29

申请人： Kenichi Akiyama ,  Yoshihiro Kotani ,  Hiroko Sehata ,  Kouichi Kotera

发明人： Kenichi Akiyama ,  Yoshihiro Kotani ,  Hiroko Sehata ,  Kouichi Kotera

IPC分类号： G06F3/038

CPC分类号： G09G3/20 ,  G02F1/13306 ,  G09G3/36

摘要： A decoder circuit which outputs a voltage based on a 8-bit digital value includes: a first decoder circuit and a second decoder circuit which output one voltage respectively using upper-order 6 bits of the 8-bit digital value; a selection circuit which receives voltages outputted from the first decoder circuit and the second decoder circuit, and distributes the two voltages to three terminals; and an intermediate voltage output circuit which outputs an intermediate voltage which is a one of five kinds of values based on the three voltages. The first decoder circuit and the second decoder circuit respectively include a select-switch-type decoder circuit and a tournament-type decoder circuit. Due to such a constitution, it is possible to reduce a circuit scale of the decoder circuit which outputs the voltage corresponding to the 8-bit digital value.

摘要翻译： 输出基于8位数字值的电压的解码器电路包括：分别使用8位数字值的高位6位输出一个电压的第一解码器电路和第二解码器电路; 接收从第一解码器电路和第二解码器电路输出的电压并将两个电压分配给三个端子的选择电路; 以及中间电压输出电路，其基于三个电压输出作为五种值中的一种的中间电压。 第一解码器电路和第二解码器电路分别包括选择开关型解码器电路和比赛型解码器电路。 由于这样的结构，可以减小输出对应于8位数字值的电压的解码器电路的电路规模。

公开(公告)号：US20120162170A1

公开(公告)日：2012-06-28

申请号：US13334280

申请日：2011-12-22

申请人： Takahiro OCHIAI ,  Mitsuru GOTO ,  Hiroyuki HIGASHIJIMA ,  Yoshihiro KOTANI ,  Shuuichirou MATSUMOTO

发明人： Takahiro OCHIAI ,  Mitsuru GOTO ,  Hiroyuki HIGASHIJIMA ,  Yoshihiro KOTANI ,  Shuuichirou MATSUMOTO

IPC分类号： G09G5/00 ,  G11C19/00

CPC分类号： G11C19/287 ,  G09G3/3677 ,  G09G5/003 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2330/021

摘要： A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V (n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.

摘要翻译： 提供能够在两个方向上执行稳定的移位操作的双向移位寄存器和使用其的图像显示装置。 在正向移位操作中，当参考点N1处于H电平时，作为双向移位寄存器的后级的第（n + 4）单位寄存器电路与时钟脉冲V（n + 4）同步地输出脉冲G（n + 4）输入到第（n + 4）个单元寄存器电路。 不仅在反向开始时产生反向触发信号VSTB，而且例如在紧接在G（n + 4）之后的单相时钟的周期（时刻t4〜t5）中垂直输出 向前移位的消隐间隔。 反向触发信号VSTB被输入到在第（n + 4）个单位寄存器电路的参考点N1设置为H电平的晶体管的栅极上，在反向启动时为止。

公开(公告)号：US20100245320A1

公开(公告)日：2010-09-30

申请号：US12700787

申请日：2010-02-05

申请人： Kenichi Akiyama ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Kenichi Akiyama ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G09G5/00

CPC分类号： G09G3/3688 ,  G09G2310/027

摘要： An object of the invention is to reduce the size of a decoder circuit of a display device. A decoder circuit which outputs voltages corresponding to 8-bit digital values includes a predecoder section, which includes an A decoder, B decoder, and C decoder, each of which is configured of a matrix type decoder circuit which carries out a three bits' worth of decoding, and a tournament type decoder circuit which carries out a three bits' worth of decoding, a selection circuit which, having input thereinto three voltages output respectively from the A decoder, B decoder, and C decoder, and applied to three output signal lines, selects two voltages of the three input voltages using a bit with one of the digital values and applies them to two output signal lines, and an intermediate voltage output circuit which, having input thereinto the two voltages selected by the selection circuit, outputs a voltage which is the average of the two voltages.

摘要翻译： 本发明的目的是减小显示装置的解码器电路的尺寸。 输出对应于8位数字值的电压的解码器电路包括预解码器部分，其包括A解码器，B解码器和C解码器，每个解码器部分由执行三比特值的矩阵型解码器电路 的解码，以及执行三比特解码的比赛型解码器电路，选择电路，其输入分别从A解码器，B解码器和C解码器输出的三个电压，并且应用于三个输出信号 使用具有数字值之一的位选择三个输入电压的两个电压，并将其施加到两个输出信号线，并且输入其中由选择电路选择的两个电压的中间电压输出电路输出一个 电压是两个电压的平均值。

公开(公告)号：US06431087B1

公开(公告)日：2002-08-13

申请号：US09701573

申请日：2001-01-24

申请人： Yoshihiro Kotani

发明人： Yoshihiro Kotani

IPC分类号： A47B3700

CPC分类号： A47B21/0314 ,  A47B21/00

摘要： A coordinate input device containing system table having a table portion for mounting thereon a monitor, a computer body and the like. The table portion includes a front table surface portion of flat and seamless as a whole, a top board having an accommodating portion formed to accommodate the coordinate input device in a lower level than the front table surface portion in a state of readiness to use, and a holding member fixed to the table portion at a reverse side thereof to support and fix the coordinate input device accommodated in the accommodated portion formed in the top board.

摘要翻译： 一种包含系统表的坐标输入装置，其具有用于在其上安装监视器，计算机主体等的台部。 台面部分包括整体平坦且无缝的前台面部分，顶板具有形成为在准备使用的状态下将坐标输入装置容纳在比前台面部分低的位置上的容纳部分，以及 保持构件在其反面固定到台部，以支撑和固定容纳在形成在顶板中的容纳部分中的坐标输入装置。

公开(公告)号：US08638284B2

公开(公告)日：2014-01-28

申请号：US12761423

申请日：2010-04-16

申请人： Yoshihiro Kotani ,  Mitsuru Goto

发明人： Yoshihiro Kotani ,  Mitsuru Goto

IPC分类号： G09G3/36

CPC分类号： G09G3/3677 ,  G11C19/184 ,  G11C19/28

摘要： A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.

摘要翻译： 提供了能够长时间抑制归因于元件的元素的劣化的栅极信号线驱动电路和显示装置，并且可以实现元件的使用寿命的延长。 对于长时间施加高电压的元件，多个元件并联连接，并且多个元件中的至少一些元件由开关元件驱动。

公开(公告)号：US08576214B2

公开(公告)日：2013-11-05

申请号：US12709254

申请日：2010-02-19

申请人： Hiroko Sehata ,  Kouichi Kotera ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

发明人： Hiroko Sehata ,  Kouichi Kotera ,  Yoshihiro Kotani ,  Shuuichirou Matsumoto

IPC分类号： G06F3/038 ,  G09G3/36

CPC分类号： H03F3/345 ,  G09G2310/027 ,  G09G2310/0297 ,  H03F3/45179

摘要： A circuit that obtains a more accurate, output voltage from a plurality of input voltages is provided. A two-input single-output circuit includes a current source transistor allowing a predetermined current to flow, a cascode transistor section including two MOS transistors that are cascode-connected to the drain side of the current source transistor and have the same characteristics, a differential pair section having a first differential pair formed of a first input-side transistor and a first output-side transistor whose source lines are shared and a second differential pair formed of a second input-side transistor and a second output-side transistor whose source lines are shared, and a current mirror circuit section. Drain lines of the transistors of the cascade transistor section are respectively connected to the source lines of the first and second differential pairs.

摘要翻译： 提供从多个输入电压获得更精确的输出电压的电路。 双输入单输出电路包括允许预定电流流动的电流源晶体管，共源共栅晶体管部分，其包括共源共栅式连接到电流源晶体管的漏极侧并具有相同特性的两个MOS晶体管，差分 所述第一差分对具有由第一输入侧晶体管和源极线共享的第一输出侧晶体管和由第二输入侧晶体管和第二输出侧晶体管形成的第二差分对形成的第一差分对， 被共享，并且是电流镜电路部分。 级联晶体管部分的晶体管的漏极线分别连接到第一和第二差分对的源极线。

公开(公告)号：US20120154359A1

公开(公告)日：2012-06-21

申请号：US13316652

申请日：2011-12-12

申请人： Takeshi SHIBATA ,  Yoshihiro Kotani ,  Shouji Nagao

发明人： Takeshi SHIBATA ,  Yoshihiro Kotani ,  Shouji Nagao

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3655 ,  G02B27/2214 ,  G09G2300/023 ,  G09G2300/0426 ,  G09G2320/0247 ,  G09G2330/021 ,  G09G2330/025 ,  H04N13/31 ,  H04N13/398

摘要： The stereoscopic display device has a display panel, a barrier liquid crystal panel disposed on the display panel, and a driving circuit for driving the display panel and the barrier liquid crystal panel, in which the frame frequency of the display panel and the alternating frequency of the barrier liquid crystal panel are different, the barrier liquid crystal panel is driven by a driving voltage input from the driving circuit, the driving circuit has an inverter circuit for outputting the driving voltage, independently controls a p-type transistor and an n-type transistor in the inverter circuit, and has time periods in which both the p-type transistor and the n-type transistor are turned off when the driving voltage is switched from a high level to a low level or a low level to a high level.

摘要翻译： 立体显示装置具有显示面板，设置在显示面板上的阻挡液晶面板和用于驱动显示面板和屏障液晶面板的驱动电路，其中显示面板的帧频和交替频率 阻挡液晶面板不同，阻挡液晶面板由从驱动电路输入的驱动电压驱动，驱动电路具有用于输出驱动电压的逆变器电路，独立地控制p型晶体管和n型 晶体管，并且当驱动电压从高电平切换到低电平或低电平至高电平时，具有p型晶体管和n型晶体管都截止的时间段。

公开(公告)号：US20100265243A1

公开(公告)日：2010-10-21

申请号：US12761423

申请日：2010-04-16

申请人： Yoshihiro KOTANI ,  Mitsuru Goto

发明人： Yoshihiro KOTANI ,  Mitsuru Goto

IPC分类号： G09G5/00

CPC分类号： G09G3/3677 ,  G11C19/184 ,  G11C19/28

摘要： A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.

摘要翻译： 提供了能够长时间抑制归因于元件的元素的劣化的栅极信号线驱动电路和显示装置，并且可以实现元件的使用寿命的延长。 对于长时间施加高电压的元件，多个元件并联连接，并且多个元件中的至少一些元件由开关元件驱动。

公开(公告)号：US20080218149A1

公开(公告)日：2008-09-11

申请号：US11873017

申请日：2007-10-16

申请人： Yoshinori Aoki ,  Mitsuru Goto ,  Yoshihiro Kotani

发明人： Yoshinori Aoki ,  Mitsuru Goto ,  Yoshihiro Kotani

IPC分类号： H02M3/156

CPC分类号： G09G3/3696 ,  G09G2330/08

摘要： The present invention is intended to minimize an amount of charge that flows from a step-up circuit into an external input voltage terminal when the power supply is turned off. A display device includes a display panel and a drive circuit that drives pixels included in the display panel. The drive circuit includes a power circuit to which a voltage Vcc is fed. The power circuit includes: a first step-up circuit that generates a voltage DDVDH which is higher than the voltage Vcc; a means 1 that when the first step-up circuit is de-energized, connects the voltage DDVDH output terminal of the first step-up circuit to a reference voltage terminal via a resistive element during a first period; and a means 2 that connects the voltage DDVDH output terminal of the first step-up circuit to an input terminal, to which the voltage Vcc is fed, during a second period succeeding the first period.

摘要翻译： 本发明旨在最小化当电源关闭时从升压电路流入外部输入电压端子的电荷量。 显示装置包括显示面板和驱动显示面板中包含的像素的驱动电路。 驱动电路包括供给电压Vcc的电源电路。 电源电路包括：产生高于电压Vcc的电压DDVDH的第一升压电路; 一种装置1，当第一升压电路断电时，在第一时段期间经由电阻元件将第一升压电路的电压DDVDH输出端连接到参考电压端; 以及在第一时段之后的第二周期期间将第一升压电路的电压DDVDH输出端子连接到馈电电压Vcc的输入端子的装置2。