公开(公告)号：US20130153979A1

公开(公告)日：2013-06-20

申请号：US13605982

申请日：2012-09-06

Applicant: Yoo Hyun NOH ,  Jong Moo Choi ,  Young Soo Ahn

Inventor： Yoo Hyun NOH ,  Jong Moo Choi ,  Young Soo Ahn

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L27/11578 ,  H01L21/266 ,  H01L27/11582

Abstract: A three-dimensional (3-D) non-volatile memory device includes channel structures each including channel layers stacked over a substrate and extending in a first direction, wherein the channel layers include well regions, respectively, vertical gates located and spaced from each other between the channel structures, and a well pick-up line contacting on the well regions of the channel layers and extending in a second direction crossing the channel structures.

Abstract translation: 三维（3-D）非易失性存储器件包括通道结构，每个通道结构包括在衬底上堆叠并在第一方向上延伸的沟道层，其中沟道层分别包括阱区，位于彼此并且彼此间隔开的垂直栅极 在通道结构之间以及在通道层的阱区域上接触并沿与通道结构交叉的第二方向延伸的阱拾取线。

公开(公告)号：US20130163324A1

公开(公告)日：2013-06-27

申请号：US13601374

申请日：2012-08-31

Applicant: Yoo Hyun NOH

Inventor： Yoo Hyun NOH

IPC: G11C16/12 ,  G11C16/04

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C16/3427

Abstract: A semiconductor memory device includes a memory cell array including first memory cells and second memory cells connected to at least one word line, a circuit group configured to perform a pre-program operation on the first memory cells using a target voltage and a main program operation on the first memory cells and the second memory cells using a final target voltage, and a control circuit configured to set the target voltage depending on variations in threshold voltages of the first memory cells caused by the main program operation of the second memory cells.

Abstract translation: 半导体存储器件包括存储单元阵列，该存储单元阵列包括连接到至少一个字线的第一存储单元和第二存储单元，被配置为使用目标电压和主程序操作对第一存储单元执行预编程操作的电路组 在第一存储单元和第二存储单元上使用最终目标电压，以及控制电路，被配置为根据由第二存储单元的主程序操作引起的第一存储单元的阈值电压的变化来设置目标电压。