公开(公告)号：US11055458B1

公开(公告)日：2021-07-06

申请号：US16899092

申请日：2020-06-11

Applicant: Xilinx, Inc.

Inventor： Aparna Suresh ,  Tapodyuti Mandal ,  Vinayak Thonda

IPC: G06F30/00 ,  G06F30/3308 ,  G01R31/3183 ,  G06F117/08

Abstract: Verification for a design can include, for a covergroup corresponding to a variable of the design, generating a state coverage data structure specifying a plurality of transition bins. Each transition bin can include a sequence. Each sequence can specify states of the variable to be traversed in order during simulation of the design. Verification can include generating a state sequence table configured to use state values as keys and one or more of the sequences as data for the respective keys, and during simulation of the design, maintaining a sequence list specifying each sequence that is running based on sample values of the variable. Hit counts for the transition bins can be updated during the simulation.

公开(公告)号：US12271670B2

公开(公告)日：2025-04-08

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/327 ,  G06F30/3308

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

公开(公告)号：US20230252212A1

公开(公告)日：2023-08-10

申请号：US17650035

申请日：2022-02-04

Applicant: Xilinx, Inc.

Inventor： Rajvinder S. Klair ,  Dhiraj Kumar Prasad ,  Saikat Bandyopadhyay ,  Ashish Kumar Jain ,  Shiyao Ge ,  Tapodyuti Mandal ,  Miti Joshi

IPC: G06F30/333 ,  G06F30/3308 ,  G06F30/327

CPC classification number: G06F30/333 ,  G06F30/3308 ,  G06F30/327

Abstract: Testbench creation for sub-design verification can include receiving, using computer hardware, a selection of a sub-design of a circuit design. The sub-design is one of a plurality of sub-designs of the circuit design. The circuit design includes a plurality of parameter values. A list of port-level signal information is generated for the selected sub-design. The one or more parameter values of the circuit design are extracted. Switching activity of each port-level signal from the list is logged in a switching activity file while running a circuit design testbench for the circuit design with the selected sub-design in scope. From the list, the switching activity, and the one or more parameter values, a sub-design testbench for the selected sub-design is generated.

公开(公告)号：US11475199B1

公开(公告)日：2022-10-18

申请号：US17486547

申请日：2021-09-27

Applicant: Xilinx, Inc.

Inventor： Saikat Bandyopadhyay ,  Feng Cai ,  Tapodyuti Mandal ,  Vinayak Thonda ,  Sree Rohith Pulipaka

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/3308 ,  G06F117/08

Abstract: Simulating a circuit design using a data processing system includes partitioning the circuit design into a top-level design and a sub-design along a boundary defined by one or more stream channels coupling a component of the top-level design with the sub-design. The sub-design is extracted from the circuit design and replaced with a stub having a client socket. A wrapper having a server socket is added to the sub-design. The top-level design and the sub-design are compiled into respective simulation kernels. The circuit design is simulated by executing the respective simulation kernels concurrently. The respective kernels communicate over a socket connection established by the client socket and the server socket. In other aspects, the partitioning results in partitions such that one partition is simulated as software and another partition is implemented in circuitry such that the circuit design may be hardware co-simulated.