-
公开(公告)号：US09449131B2
公开(公告)日：2016-09-20
申请号：US14294062
申请日：2014-06-02
Applicant: Xilinx, Inc.
Inventor： Guoling Han , Stephen A. Neuendorffer
CPC classification number: G06F17/5045 , G06F8/433 , G06F8/45 , G06F8/452 , G06F8/456 , G06F17/505 , G06F17/5054 , G06F2217/86
Abstract: Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.
Abstract translation: 在高级合成中提取系统架构包括确定高级编程语言描述的第一函数和包含在高级编程描述的控制流结构内的第二函数。 第二功能被确定为第一功能的数据消耗功能。 在电路设计中，自动生成包括本地存储器的端口。 端口将第一功能的第一电路块实现耦合到电路设计内的第二功能的第二电路块实现。
-
公开(公告)号：US10671779B1
公开(公告)日：2020-06-02
申请号：US16030686
申请日：2018-07-09
Applicant: Xilinx, Inc.
Inventor： Stephen A. Neuendorffer
IPC: G06F30/327
Abstract: A method of high level synthesis may include detecting in an application, using computer hardware, a first function including a first call site for a second function and a second call site for the second function, determining, using the computer hardware, that the first call site and the second call site each pass different data to the second function and each receive different return data from the second function, and generating, using the computer hardware, a circuit design from the application including a circuit block implementing the second function and multiplexer circuitry. The multiplexer circuitry may be configured to coordinate passing of data to the circuit block from a first source circuit corresponding to the first call site and a second source circuit corresponding to the second call site, with handshake signals exchanged between the circuit block, the first source circuit, and the second source circuit.
-
公开(公告)号：US10031732B1
公开(公告)日：2018-07-24
申请号：US15226768
申请日：2016-08-02
Applicant: Xilinx, Inc.
Inventor： Dong Li , Sheng Zhou , Stephen A. Neuendorffer
Abstract: High level synthesis can include detecting, using a processor, an enumerated operation within an instruction of a loop construct of an application, determining, using the processor, whether the loop construct meets a modification condition, and responsive to determining that the loop construct meets the modification condition, modifying, using the processor, the loop construct to calculate the enumerated operation as a compile time constant, wherein the modified loop construct is functionally equivalent to the loop construct.
-
Patent Agency Ranking
公开(公告)号：US11422781B1
公开(公告)日：2022-08-23
申请号：US16781323
申请日：2020-02-04
Applicant: Xilinx, Inc.
Inventor： Stephen A. Neuendorffer , Prasanth Chatarasi , Samuel R. Bayliss
Abstract: Disclosed approaches for generating vector codes include inputting tensor processing statements. Each statement specifies an output variable, an initial variable, and multiply-and-accumulate (MAC) operations, and each MAC operation references the output variable, elements of a first tensor, and one or more elements of a second tensor. The MAC operations are organized into groups, and the MAC operations in each group reference the same output variable and have overlapping references to elements of the first tensor. For each group of MAC operations, at least one instruction is generated to load elements of the first tensor into a first register and at least one instruction is generated to load one or more elements of the second tensor into a second register. For each group of MAC operations, instructions are generated to select for each MAC operation in the group for input to an array of MAC circuits, elements from the first register and one or more elements from the second register.
-
公开(公告)号：US09824172B1
公开(公告)日：2017-11-21
申请号：US15078400
申请日：2016-03-23
Applicant: Xilinx, Inc.
Inventor： Kecheng Hao , Hongbin Zheng , Stephen A. Neuendorffer
IPC: G06F17/50
CPC classification number: G06F17/505
Abstract: Implementing circuitry from an application can include determining a data flow of an application including a producer function, a loop construct, and a consumer function and creating a new function including contents of a body of the loop construct. A circuit design can be generated from the application including a producer function circuit block, a new function circuit block, and a consumer function circuit block. Control circuitry for each circuit block can be included within the circuit design. The control circuitry of the new function circuit block can initiate operation of the new function circuit block according to a loop induction variable of the loop construct.
-
公开(公告)号：US09710584B1
公开(公告)日：2017-07-18
申请号：US15078347
申请日：2016-03-23
Applicant: Xilinx, Inc.
Inventor： Kecheng Hao , Hongbin Zheng , Stephen A. Neuendorffer
CPC classification number: G06F17/505 , G06F8/443
Abstract: Implementing circuitry from an application may include partitioning an array of the application into a plurality of virtual blocks according to a streaming dimension of the array and determining that a first function and a second function of the application that access the array have same access patterns for the virtual blocks of the array. A first-in-first out (FIFO) memory may be included in a circuit design implementing the application. The FIFO memory couples a first circuit block implementing the first function with a second circuit block implementing the second function. Control circuitry is included within the circuit design. The control circuitry may be configured to implement concurrent operation of the first circuit block and the second circuit block by controlling accesses of the first circuit block and the second circuit block to a plurality of buffers in the FIFO memory.
-
公开(公告)号：US20150347654A1
公开(公告)日：2015-12-03
申请号：US14294062
申请日：2014-06-02
Applicant: Xilinx, Inc.
Inventor： Guoling Han , Stephen A. Neuendorffer
IPC: G06F17/50
CPC classification number: G06F17/5045 , G06F8/433 , G06F8/45 , G06F8/452 , G06F8/456 , G06F17/505 , G06F17/5054 , G06F2217/86
Abstract: Extracting a system architecture in high level synthesis includes determining a first function of a high level programming language description and a second function contained within a control flow construct of the high level programming description. The second function is determined to be a data consuming function of the first function. Within a circuit design, a port including a local memory is automatically generated. The port couples a first circuit block implementation of the first function to a second circuit block implementation of the second function within the circuit design.
Abstract translation: 在高级合成中提取系统架构包括确定高级编程语言描述的第一函数和包含在高级编程描述的控制流结构内的第二函数。 第二功能被确定为第一功能的数据消耗功能。 在电路设计中，自动生成包括本地存储器的端口。 端口将第一功能的第一电路块实现耦合到电路设计内的第二功能的第二电路块实现。
-
公开(公告)号：US09081930B1
公开(公告)日：2015-07-14
申请号：US14450544
申请日：2014-08-04
Applicant: Xilinx, Inc.
Inventor： Stephen A. Neuendorffer , Kecheng Hao , Guoling Han
CPC classification number: G06F17/505 , G06F11/261 , G06F17/5045
Abstract: Improving throughput during high level synthesis includes determining a data dependency for a flow control construct of a high level programming language description and translating the high level programming language description into a circuit design specifying circuitry for implementation within an integrated circuit. The circuitry is pipelined. As part of the circuit design and using a processor, a stall detection circuit is generated. The stall detection circuit is coupled to selectively initiate a stall of a stalling portion of the circuitry according to the data dependency.
Abstract translation: 在高级合成期间提高吞吐量包括确定用于高级编程语言描述的流控制结构的数据依赖性，并将高级编程语言描述转换成用于在集成电路内实现的电路设计指定电路。 电路是流水线的。 作为电路设计和使用处理器的一部分，产生了失速检测电路。 失速检测电路被耦合以根据数据依赖性选择性地启动电路的停滞部分的失速。
-
-
-
-
-
-
-
Search Results
8
records
(took 0.014 seconds)
