公开(公告)号：US09270517B1

公开(公告)日：2016-02-23

申请号：US13789331

申请日：2013-03-07

Applicant: Xilinx, Inc.

Inventor： Michael E. Attig ,  Gordon J. Brebner

IPC: H04J3/00 ,  H04L29/06 ,  H04L12/851 ,  H04W28/06

CPC classification number: H04L69/22 ,  H04L47/2441 ,  H04L47/2483 ,  H04L69/04 ,  H04L69/166 ,  H04W28/06 ,  H04W28/065

Abstract: In one approach for processing a data packet, in at least one stage of a plurality of stages of a pipeline circuit, a respective packet field value is extracted from the data packet. In each stage of the plurality of stages, a respective tuple field value is inserted into a respective tuple register of the stage at a respective offset. The respective tuple field value in the at least one stage is based on the respective packet field value. In each stage of the plurality of stages except a last one of the stages, the contents of the respective tuple register of the stage are provided as input to a next one of the stages.

Abstract translation: 在处理数据分组的一种方法中，在流水线电路的多个级的至少一级中，从数据分组中提取相应的分组字段值。 在多个级的每个级中，相应的元组字段值以相应的偏移量被插入到级的相应的元组寄存器中。 至少一个阶段中的相应元组字段值基于相应的分组字段值。 在除了最后一个级之外的多个级的每个级中，将级的各个元组寄存器的内容提供给下一级的输入。