公开(公告)号：US11290361B1

公开(公告)日：2022-03-29

申请号：US16716256

申请日：2019-12-16

Applicant: Xilinx, Inc.

Inventor： Chengchen Hu ,  Ji Yang ,  Yan Zhang ,  Gordon J. Brebner ,  Siyi Qiao

IPC: H04L12/26 ,  H04L43/12 ,  H04L43/10 ,  H04L43/062 ,  H04L43/50 ,  H04L43/028

Abstract: A device includes a programmable passive measurement hardware engine, a programmable active measurement hardware engine, and a configuration engine. The programmable passive measurement hardware engine is configured to collect statistical data, from data transmission at a network line rate, used for network measurement. The programmable active measurement hardware engine is configured to generate probe packets and wherein the programmable active measurement hardware engine is further configured to collect responses to the generated probe packets, wherein the collected responses are used for the network measurement. The configuration engine is configured to receive data settings and wherein the configuration engine is further configured to program the programmable passive measurement hardware engine and the programmable active measurement hardware engine with the received data settings.

公开(公告)号：US09350385B2

公开(公告)日：2016-05-24

申请号：US13841574

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Mark B. Carson

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/09

CPC classification number: H03M13/09 ,  H03M13/091

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract translation: 公开了用于执行循环冗余校验的设备和方法。 例如，设备具有用于将数据字分割成多个路径的分离器。 该设备还具有多个循环冗余校验单元。 每个单元用于处理相应的一个路径。 另外，每个单元包括用于输出用于在单元内结束的分组的循环冗余校验值的第一输出端口和用于输出在单元内开始或正在进行的分组的循环冗余校验值的第二输出端口。

公开(公告)号：US20140281844A1

公开(公告)日：2014-09-18

申请号：US13841574

申请日：2013-03-15

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Mark B. Carson

IPC: H03M13/09

CPC classification number: H03M13/09 ,  H03M13/091

Abstract: Devices and methods for performing a cyclic redundancy check are disclosed. For example, a device has a splitter for splitting a data word into a plurality of paths. The device also has a plurality of cyclic redundancy check units. Each of the units is for processing a respective one of the paths. In addition, each of the units includes a first output port for outputting a cyclic redundancy check value for a packet ending within the unit and a second output port for outputting a cyclic redundancy check value for a packet starting or ongoing within the unit.

Abstract translation: 公开了用于执行循环冗余校验的设备和方法。 例如，设备具有用于将数据字分割成多个路径的分离器。 该设备还具有多个循环冗余校验单元。 每个单元用于处理相应的一个路径。 另外，每个单元包括用于输出用于在单元内结束的分组的循环冗余校验值的第一输出端口和用于输出在单元内开始或正在进行的分组的循环冗余校验值的第二输出端口。

公开(公告)号：US11425036B1

公开(公告)日：2022-08-23

申请号：US16386127

申请日：2019-04-16

Applicant: Xilinx, Inc.

Inventor： Jaime Herrera ,  Gordon J. Brebner ,  Ian McBryan ,  Rowan Lyons

IPC: H04L45/74 ,  H04L69/22 ,  H04L47/56 ,  H04L45/24

Abstract: A match-action circuit includes one or more conditional logic circuits, each having an input coupled to input header or metadata of a network packet, and each configured to generate an enable signal as a function of one or more signals of the header or metadata. Each match circuit of one or more match circuits is configured with response values associated with key values. Each match circuit is configured to conditionally lookup response value(s) associated with an input key value from the header or metadata in response to the enable signal from a conditional logic circuit. One or more action circuits are configured to conditionally modify, in response to states of the response value(s) output from the match circuit(s), data of the header or the metadata.

公开(公告)号：US09110524B1

公开(公告)日：2015-08-18

申请号：US14299736

申请日：2014-06-09

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner ,  Yi-Hua Yang

IPC: H03K19/173 ,  G06F1/04 ,  G05B19/045

CPC classification number: G06F1/04 ,  G05B19/045 ,  G05B2219/23289 ,  G06F1/10

Abstract: In an FSM circuit, look-ahead-cascade modules are coupled to receive possible states and corresponding subsets of data inputs. Merge modules are coupled to a second-to-the-lowest to highest order of the look-ahead-cascade modules. The second-to-the-lowest to highest order of disambiguation modules are coupled to at least a portion of the merge modules. The lowest order of the disambiguation modules is coupled to the lowest order of the look-ahead-cascade modules. The lowest-to-highest order of the disambiguation modules are coupled to receive respective sets of interim states of rN states each to select respective sets of next states of r states each. A state register is coupled to receive a portion of the highest order of the sets of next states to provide a select signal. Each of the disambiguation modules is coupled to receive the select signal for selection of the sets of next states of the r states each.

Abstract translation: 在FSM电路中，先行级联模块被耦合以接收可能的状态和相应的数据输入子集。 合并模块耦合到先行级联模块的第二到最低级别。 消歧模块的第二到最低到最高顺序耦合到合并模块的至少一部分。 消歧模块的最低顺序与先行级联模块的最低级联联。 消歧模块的最低到最高顺序被耦合以接收各自的rN状态的各个中间状态集合，以各自选择各状态的下一个状态。 状态寄存器被耦合以接收下一状态组的最高阶的一部分以提供选择信号。 每个消歧模块被耦合以接收选择信号，用于选择各状态的下一个状态的集合。

公开(公告)号：US10834241B1

公开(公告)日：2020-11-10

申请号：US16242876

申请日：2019-01-08

Applicant: Xilinx, Inc.

Inventor： Ian McBryan ,  Gordon J. Brebner ,  Jaime Herrera ,  Rowan Lyons

IPC: H04J3/24 ,  H04L29/06 ,  H04L12/723

Abstract: Apparatus and associated methods relating to data packet deparsing include an editing circuit configured to perform one or more predetermined editing operations on headers of an incoming data packet step by step without extracting all headers from the incoming data packet. In an illustrative example, an editor circuit may include an updating circuit configured to receive the data packet and update a header in the data packet. The editor circuit may also include a removal circuit configured to remove a header from the data packet. The editor circuit may also include an insertion circuit configured to insert one or more consecutive headers to the data packet. A state machine may be configured to enable or disable the updating circuit, the removal circuit, and/or the insertion circuit based on the predetermined editing operations. By using the editing circuit, packet deparsing may be performed with less hardware resources and low latency.

公开(公告)号：US09674081B1

公开(公告)日：2017-06-06

申请号：US14705907

申请日：2015-05-06

Applicant: Xilinx, Inc.

Inventor： Weirong Jiang ,  Gordon J. Brebner

IPC: H04L12/721 ,  H04L12/24 ,  H04L12/741

CPC classification number: H04L45/38 ,  H04L41/0803 ,  H04L45/745

Abstract: Methods and apparatus for using dynamic programming to determine the most efficient mapping of a pipeline of virtual flow tables (VFTs) onto a pipeline of physical flow tables (PFTs) in the data plane of a software-defined networking (SDN) device are described. One example method of determining a configuration for an SDN device generally includes receiving a representation of a series of one or more VFTs, each of the VFTs having one or more properties; receiving a representation of a series of one or more PFTs for hardware of the SDN device, each of the PFTs having one or more capabilities; generating, using dynamic programming based on the properties of the VFTs and the capabilities of the PFTs, a mapping of the series of VFTs onto the series of PFTs; and outputting the generated mapping for implementation on the hardware of the SDN device.

公开(公告)号：US11831743B1

公开(公告)日：2023-11-28

申请号：US16242860

申请日：2019-01-08

Applicant: Xilinx, Inc.

Inventor： Jaime Herrera ,  Gordon J. Brebner ,  Ian McBryan ,  Rowan Lyons

IPC: H04L69/22 ,  H04L69/324

CPC classification number: H04L69/22 ,  H04L69/324

Abstract: Apparatus and associated methods relate to packet header field extraction as defined by a high level language and implemented in a minimum number of hardware streaming parsing stages to speculatively extract header fields from among multiple possible header sequences. In an illustrative example, the number of stages may be determined from the longest possible header sequence in any received packet. For each possible header sequence, one or more headers may be assigned to each stage, for example, based on a parse graph. Each pipelined stage may resolve a correct header sequence, for example, by sequentially extracting length and transition information from an adjacent prior stage to determine offset of the next header. By speculatively extracting selected fields from every possible position in each pipeline stage, a correct value may be selected using sequential hardware streaming pipelines to substantially reduce parsing latency.

公开(公告)号：US11431815B1

公开(公告)日：2022-08-30

申请号：US16869321

申请日：2020-05-07

Applicant: Xilinx, Inc.

Inventor： Guanwen Zhong ,  Haris Javaid ,  Chengchen Hu ,  Ji Yang ,  Gordon J. Brebner

IPC: H04L67/56 ,  H04L69/16 ,  H04L45/302 ,  H04L45/16 ,  H04L69/324

Abstract: Mining proxy acceleration may include receiving, within a mining proxy, packetized data from a mining pool server and determining, using the mining proxy, whether the packetized data qualifies for broadcast processing. In response to determining that the packetized data qualifies for broadcast processing, the packetized data can be modified using the mining proxy to generate broadcast data. The broadcast data can be broadcast, using the mining proxy, to a plurality of miners subscribed to the mining proxy.

公开(公告)号：US09270517B1

公开(公告)日：2016-02-23

申请号：US13789331

申请日：2013-03-07

Applicant: Xilinx, Inc.

Inventor： Michael E. Attig ,  Gordon J. Brebner

IPC: H04J3/00 ,  H04L29/06 ,  H04L12/851 ,  H04W28/06

CPC classification number: H04L69/22 ,  H04L47/2441 ,  H04L47/2483 ,  H04L69/04 ,  H04L69/166 ,  H04W28/06 ,  H04W28/065

Abstract: In one approach for processing a data packet, in at least one stage of a plurality of stages of a pipeline circuit, a respective packet field value is extracted from the data packet. In each stage of the plurality of stages, a respective tuple field value is inserted into a respective tuple register of the stage at a respective offset. The respective tuple field value in the at least one stage is based on the respective packet field value. In each stage of the plurality of stages except a last one of the stages, the contents of the respective tuple register of the stage are provided as input to a next one of the stages.

Abstract translation: 在处理数据分组的一种方法中，在流水线电路的多个级的至少一级中，从数据分组中提取相应的分组字段值。 在多个级的每个级中，相应的元组字段值以相应的偏移量被插入到级的相应的元组寄存器中。 至少一个阶段中的相应元组字段值基于相应的分组字段值。 在除了最后一个级之外的多个级的每个级中，将级的各个元组寄存器的内容提供给下一级的输入。