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公开(公告)号：US09313078B1
公开(公告)日：2016-04-12
申请号：US14682737
申请日：2015-04-09
Applicant: Xilinx, Inc.
Inventor： Kaushik Barman , Gregory C. Copeland
CPC classification number: H04L27/2624
Abstract: A method relates generally to data transmission. In such a method, a peak detector detects a signal peak of an input signal exceeding a threshold amplitude. This detecting includes sampling the input signal at a sampling frequency to provide a sampled signal. The sampling frequency is in a range greater than a bandwidth frequency of a carrier signal used for providing the input signal and less than twice the bandwidth frequency. Samples of the sampled signal proximate to the signal peak are interpolated to provide a reconstructed peak. A cancellation pulse is applied by a cancellation pulse generator to the samples to reduce the signal peak. A version of the input signal is output after application of the cancellation pulse.
Abstract translation: 一种方法一般涉及数据传输。 在这种方法中，峰值检测器检测超过阈值振幅的输入信号的信号峰值。 该检测包括以采样频率采样输入信号以提供采样信号。 采样频率在大于用于提供输入信号的载波信号的带宽频率的范围内，并且小于带宽频率的两倍。 插值到信号峰值附近的采样信号的样本被内插以提供重建的峰值。 取消脉冲由消除脉冲发生器施加到样本以减小信号峰值。 在应用取消脉冲之后输出输入信号的一个版本。
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公开(公告)号：US11113030B1
公开(公告)日：2021-09-07
申请号：US16420905
申请日：2019-05-23
Applicant: Xilinx, Inc.
Inventor： Dinesh K. Monga , Shail Aditya Gupta , Samuel R. Bayliss , Kaushik Barman
Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bitstream and/or binary code which configures programmable and non-programmable logic in a heterogeneous processing environment of a SoC to execute the graph. The compiler can also consider user-defined constraints when compiling the source code. The constraints can dictate where the kernels and buffers should be placed in the heterogeneous processing environment, performance requirements, data communication routes through the SoC, type of data path, delays, and the like.
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公开(公告)号：US20200076660A1
公开(公告)日：2020-03-05
申请号：US16117605
申请日：2018-08-30
Applicant: Xilinx, Inc.
Inventor： Kaushik Barman , Parag Dighe , Baris Ozgul , Sneha Bhalchandra Date
Abstract: Techniques related to a data processing engine for an integrated circuit (IC) are described. In an example, a method is provided for vectorized peak detection. The method includes dividing a set of data samples of a data signal, corresponding to a peak detection window (PDW), into a plurality of subsets of data samples each comprising a number of data samples. The method includes performing vector operations on each of the plurality of subsets of data samples. The method includes determining a running index of a sample with a maximum amplitude over the PDW based on the vector operations.
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公开(公告)号：US20230297824A1
公开(公告)日：2023-09-21
申请号：US17655489
申请日：2022-03-18
Applicant: Xilinx, Inc.
Inventor： Rajeev Patwari , Chaithanya Dudha , Jorn Tuyls , Kaushik Barman , Aaron Ng
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: A programmable, non-linear (PNL) activation engine for a neural network is capable of receiving input data within a circuit. In response to receiving an instruction corresponding to the input data, the PNL activation engine is capable of selecting a first non-linear activation function from a plurality of non-linear activation functions by decoding the instruction. The PNL activation engine is capable of fetching a first set of coefficients corresponding to the first non-linear activation function from a memory. The PNL activation engine is capable of performing a polynomial approximation of the first non-linear activation function on the input data using the first set of coefficients. The PNL activation engine is capable of outputting a result from the polynomial approximation of the first non-linear activation function.
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