公开(公告)号：US20240330558A1

公开(公告)日：2024-10-03

申请号：US18193197

申请日：2023-03-30

Applicant: Xilinx, Inc.

Inventor： Jichun Wang ,  Wuxi Li ,  Chun Zhang ,  Paul Kundarewich ,  John Blaine

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Implementing circuit designs in integrated circuit devices includes determining, using computer hardware, regular control sets, super control sets, and mega control sets for a circuit design. Control set optimization is performed on the circuit design. Performing control set optimization includes performing a clock-enable-only control set reduction for each super control set. Performing control set optimization includes performing a set/reset control set reduction and a clock-enable control set reduction for each mega control set. The circuit design is selectively modified by committing changes determined from the control set reductions to the circuit design on a per control set basis based on an improvement of a cost metric for each control set.

公开(公告)号：US11714950B2

公开(公告)日：2023-08-01

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/392 ,  G06F30/398 ,  G06F30/327 ,  G06F30/31

CPC classification number: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.

公开(公告)号：US20230034736A1

公开(公告)日：2023-02-02

申请号：US17382621

申请日：2021-07-22

Applicant: Xilinx, Inc.

Inventor： Veeresh Pratap Singh ,  Meghraj Kalase ,  John Blaine ,  Srinivasan Dasasathyan ,  Padmini Gopalakrishnan ,  Frederic Revenu ,  Veena Johar ,  Pawan Kumar Singh ,  Mohit Sharma ,  Kameshwar Chandrasekar

IPC: G06F30/398 ,  G06F30/31 ,  G06F30/327 ,  G06F30/392

Abstract: Processing a circuit design includes stabilizing the circuit design by a design tool that performs one or more iterations of implementation, optimization assessment, optimization, and stability assessment until a threshold stability level is achieved. The design tool determines, in response to satisfaction of the threshold stability level, different strategies based on features of the circuit design and likelihood that use of the strategies would improve timing. Each strategy includes parameter settings for the design tool. The design tool executes multiple implementation flows using different sets of strategies to generate alternative implementations. One implementation of the alternative implementations nearest to satisfying a timing requirement is selected. The selected implementation is iteratively optimized to satisfy the timing requirement, while restricting changes to placement of cells and nets on a critical path of the one implementation to less than a threshold portion of cells and nets on the critical path.