公开(公告)号：US09666248B1

公开(公告)日：2017-05-30

申请号：US14885709

申请日：2015-10-16

Applicant: Xilinx, Inc.

Inventor： Edward S. Peterson

IPC: G11C16/04 ,  G11C7/10 ,  G11C7/24 ,  G11C16/22 ,  G11C16/10

CPC classification number: G11C7/10 ,  G11C7/24 ,  G11C16/0433 ,  G11C16/10 ,  G11C16/22 ,  G11C17/16 ,  H03K19/177

Abstract: A programmable integrated circuit, includes an external port, a configuration memory, a hardened write path between the external port and the configuration memory and a soft read path between the configuration memory and the external port, wherein configuration data stored in the configuration memory is only read through the soft read path.

公开(公告)号：US09218505B1

公开(公告)日：2015-12-22

申请号：US13756151

申请日：2013-01-31

Applicant: Xilinx, Inc.

Inventor： James D. Wesselkamper ,  James B. Anderson ,  Jason J. Moore ,  Edward S. Peterson

IPC: G06F21/00 ,  G06F21/72

CPC classification number: G06F21/72 ,  G06F21/755 ,  H04L9/003 ,  H04L9/3239

Abstract: Approaches for configuring a programmable integrated circuit (IC) are disclosed. Encrypted configuration data is input to the programmable IC, and the encrypted configuration data is stored in configuration memory of the programmable IC. As the encrypted configuration data is input, a determination is made as to whether or not the encrypted configuration data is authentic. In response to the encrypted configuration data being authentic, the encrypted configuration data is read from the configuration memory and decrypted, and the decrypted configuration data is stored back in the configuration memory.

Abstract translation: 公开了用于配置可编程集成电路（IC）的方法。 加密的配置数据被输入到可编程IC，并且加密的配置数据被存储在可编程IC的配置存储器中。 当输入加密配置数据时，确定加密配置数据是否可信。 响应于加密的配置数据是可信的，从配置存储器中读取加密的配置数据并进行解密，并将解密的配置数据存储在配置存储器中。

公开(公告)号：US10978167B1

公开(公告)日：2021-04-13

申请号：US16806546

申请日：2020-03-02

Applicant: Xilinx, Inc.

Inventor： James D. Wesselkamper ,  Edward S. Peterson ,  Jason J. Moore ,  Steven E. McNeil

IPC: G11C17/00 ,  G11C17/16 ,  G11C17/18

Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.

公开(公告)号：US11579957B1

公开(公告)日：2023-02-14

申请号：US16938764

申请日：2020-07-24

Applicant: Xilinx, Inc.

Inventor： Edward S. Peterson ,  Trevor W. Hardcastle ,  Carl H. Carmichael

IPC: G06F11/07 ,  G06F11/30 ,  G06F11/34

Abstract: A system includes a plurality of watchdog components. Each watchdog component is configured to receive a kick signal from its monitored function to determine whether the monitored function is active. Each watchdog component is further configured to receive a respective token from all watchdog components that the each watchdog component is connected to. The respective token determines whether its respective watchdog component has timed out. Each watchdog component is further configured to generate a token responsive to the kick signal and further responsive to the respective token from all watchdog component that the each watchdog component is connected to. Each watchdog component is further configured to transmit the generated token to the all watchdog components that the each watchdog component is connected to.

公开(公告)号：US11379580B1

公开(公告)日：2022-07-05

申请号：US16819864

申请日：2020-03-16

Applicant: Xilinx, Inc.

Inventor： James D. Wesselkamper ,  Edward S. Peterson ,  Jason J. Moore ,  Steven E. McNeil ,  Roger D. Flateau, Jr. ,  Danny Tsung-Heng Wu ,  Boon Y. Ang

IPC: G06F21/55 ,  G06F21/72 ,  H04L9/32 ,  G11C29/00 ,  G11C29/08

Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

公开(公告)号：US11280829B1

公开(公告)日：2022-03-22

申请号：US16721843

申请日：2019-12-19

Applicant: Xilinx, Inc.

Inventor： Ramakrishna G. Poolla ,  Krishna C. Patakamuri ,  James D. Wesselkamper ,  Jason J. Moore ,  Edward S. Peterson ,  Steven E. McNeil

IPC: H04L29/06 ,  G01R31/317 ,  G01R31/3177 ,  G06F21/44 ,  H04L9/32 ,  G06F21/76 ,  H04L9/30

Abstract: Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.

公开(公告)号：US10044514B1

公开(公告)日：2018-08-07

申请号：US14866712

申请日：2015-09-25

Applicant: Xilinx, Inc.

Inventor： Edward S. Peterson ,  James D. Wesselkamper

IPC: G06F11/30 ,  H04L9/32 ,  H04L9/14

Abstract: The disclosure describes approaches for protecting a circuit design for a programmable integrated circuit (IC). A black key is generated from an input red key by a registration circuit implemented on the programmable IC, and the black key is stored in a memory circuit external to the programmable IC. The programmable IC is configured to implement a pre-configuration circuit, which inputs the black key from the memory circuit and generates the red key from the black key. A ciphertext circuit design is decrypted into a plaintext circuit design by the programmable IC using the red key, and the red key is erased from the programmable IC. The programmable IC is reconfigured with the plaintext circuit design.

公开(公告)号：US09230112B1

公开(公告)日：2016-01-05

申请号：US13775151

申请日：2013-02-23

Applicant: Xilinx, Inc.

Inventor： Edward S. Peterson ,  Roger D. Flateau, Jr. ,  James D. Wesselkamper ,  Steven E. McNeil ,  Jason J. Moore ,  Lester S. Sanders ,  Lawrence C. Hung ,  Yatharth K. Kochar

IPC: G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  G06F9/44 ,  G06F21/76

CPC classification number: G06F21/575 ,  G06F9/4401 ,  G06F9/4406 ,  G06F9/4416 ,  G06F21/76

Abstract: A system generally relating to an SoC, which may be a field programmable SoC (“FPSoC”), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Abstract translation: 通常涉及可能是现场可编程SoC（“FPSoC”）的SoC的系统被公开。 在该SoC中，专用硬件包括处理单元，第一内部存储器，第二内部存储器，认证引擎和解密引擎。 存储设备耦合到SoC。 存储设备可以访问引导映像。 第一内部存储器具有存储在其中的引导代码。 引导代码用于安全引导SoC。 引导代码被配置为使处理单元控制安全启动。