公开(公告)号：US20240330213A1

公开(公告)日：2024-10-03

申请号：US18191353

申请日：2023-03-28

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Tao Yu ,  Chiranjeevi Sirandas ,  Nicholas Trank

IPC: G06F13/16 ,  G06F9/30

CPC classification number: G06F13/1673 ,  G06F9/30047 ,  G06F13/1626

Abstract: Descriptor fetch for a direct memory access system includes, in response to receiving a first data packet, fetching a plurality of descriptors including a first descriptor and a specified number of prefetched descriptors. The plurality of descriptors specify different buffer sizes. In response to processing each data packet, selectively replenishing the plurality of fetched descriptors to the specified number of prefetched descriptors.

公开(公告)号：US20240330215A1

公开(公告)日：2024-10-03

申请号：US18191365

申请日：2023-03-28

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Tao Yu ,  Chiranjeevi Sirandas ,  Nicholas Trank

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: Descriptor fetch for a direct memory access system includes obtaining a descriptor for processing a received data packet. A determination is made as to whether the descriptor is a head descriptor of a chain descriptor. In response to determining that the descriptor is a head descriptor, one or more tail descriptors are fetched from a descriptor table specified by the head descriptor. A number of the tail descriptors fetched is determined based on a running count of a buffer size of the chain descriptor determined as each tail descriptor is fetched compared to a size of the data packet.