公开(公告)号：US09774866B1

公开(公告)日：2017-09-26

申请号：US14639405

申请日：2015-03-05

Applicant: Xilinx, Inc.

Inventor： Venkata V. Dhanikonda ,  Arun Ananthapadmanaban

IPC: H04N19/146 ,  H04N7/12 ,  H04L12/861

CPC classification number: H04N19/146 ,  G09G5/006 ,  G09G5/008 ,  G09G5/12 ,  G09G2320/0693 ,  G09G2320/08 ,  G09G2370/10 ,  H04L7/0012 ,  H04L25/14 ,  H04L49/90 ,  H04N7/12 ,  H04N21/4305

Abstract: A video processing system can include a buffer, a packetizer block that is coupled to the buffer, and a buffer controller that is coupled to the buffer and the packetizer block. The buffer is capable of receiving and storing a video signal as video data. The packetizer block is capable of packetizing video data read from the buffer and sending packetized data to a node external to the video processing system. The buffer controller is capable of controlling an amount of video data included within each packet generated by the packetizer block.