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公开(公告)号:US20180188587A1
公开(公告)日:2018-07-05
申请号:US15327996
申请日:2016-07-14
Inventor: Xin QIU , Yao-li HUANG
IPC: G02F1/1333 , G02F1/1362 , G02F1/1335 , H01L27/12
CPC classification number: G02F1/133305 , G02F1/133 , G02F1/133514 , G02F1/13454 , G02F1/1362 , G02F1/136204 , G02F2001/133311 , G02F2001/13456 , G02F2201/50 , H01L27/1214 , H01L27/1218 , H01L27/1262
Abstract: The present invention provides a thin film transistor (TFT) array substrate which includes: a substrate; a display region formed on the substrate; a flexible printed circuit disposed on the substrate and located at one side of the display region; a control chip disposed between the display region and the flexible printed circuit, and two sides of the flexible printed circuit going beyond two corresponding sides of the control chip, respectively; a first reinforcement member disposed at a first side of the control chip, and the first side being adjacent to one side of the control chip that faces the display region; a second reinforcement member disposed at a second side of the control chip opposite to the first side; and a third reinforcement member covering the control chip, the first reinforcement member and the second reinforcement member.
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2.
公开(公告)号:US20180203290A1
公开(公告)日:2018-07-19
申请号:US15301225
申请日:2016-06-27
Inventor: Xin QIU , Shihpo CHOU
IPC: G02F1/1335 , G02F1/1333 , G02F1/1339 , G06F3/041
CPC classification number: G02F1/133514 , G02F1/13338 , G02F1/133512 , G02F1/1339 , G02F2001/133357 , G02F2202/16 , G02F2202/28 , G06F3/0412
Abstract: The present application discloses a liquid crystal panel, includes a CF substrate forms a display and a non-display region; the CF substrate including a plurality of color resist modules and a planarization layer, the plurality of color resist modules is arranged in a matrix within the display region, the planarization layer including a shielding layer and a plurality of the first color resist connected to the shielding layer, the plurality of the first color resist and the color resist modules are alternately arranged in the display region, the shielding layer is covering the plurality of the color resist modules, a conducting polymer is added in the planarization layer; an array substrate includes a grounding pad disposed facing to the non-display region; a conductive particle is added in the sealant and the sealant is connected to the planarization layer and the grounding pad to make the planarization layer connecting to ground.
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