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1.发明授权公开(公告)号：US10714504B2
公开(公告)日：2020-07-14
申请号：US16308824
申请日：2018-11-20
Inventor： Chen Chen
Abstract: The present disclosure proposes a method of producing an LTPS TFT array substrate. The method is about stacking of a gate insulating layer and an interlayer insulating layer for providing conditions for formation of a gate trench. In addition, stacking of the gate insulating layer and the interlayer insulating layer is produced with some blocks of forming a hole on the gate insulating layer and the interlayer insulating layer to form a hole pattern, filling the gate trench, and producing gate lines. In this way, the formation of the gate lines and the formation of the hole pattern on the gate insulating layer and the interlayer insulating layer are done using the same mask. The method of the present disclosure reduces the number of masks required compared with the method of the related art, thereby reducing the production costs.
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公开(公告)号：US20180323217A1
公开(公告)日：2018-11-08
申请号：US15523001
申请日：2017-03-14
Inventor： Chen Chen
IPC: H01L27/12 , G02F1/1362 , H01L27/02
CPC classification number: H01L27/124 , G02F1/133512 , G02F1/136286 , G02F1/1368 , H01L27/0207 , H01L27/1222
Abstract: Disclosed is a distribution of TFT components in the LTPS process. A pair of parallel data lines are arranged between an ith and (i+1)th rows of pixels. Each pair of data lines includes a first data line and a second data line. Two adjacent pixels of the ith row are respectively connected to the first data line and the second data line through corresponding U-shaped TFT components. Two pixels of the (n+1)th row corresponding to the two above adjacent pixels are respectively connected to the second data line and the first data line through corresponding U-shaped TFT components. The U-shaped TFT component of the pixel of the ith row and the U-shaped TFT component of the corresponding pixel of the (i+1)th row are disposed with openings thereof facing and staggered with each other. An aperture ratio of a product can be effectively increased by the staggered setting of the U-shaped TFT components. The use of such setting can realize dot inversion in the case of column inversion and reduce the power consumption of the product.
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Patent Agency Ranking
公开(公告)号：US10658402B2
公开(公告)日：2020-05-19
申请号：US15737131
申请日：2017-09-21
Inventor： Chen Chen
IPC: H01L27/12 , H01L21/77 , H01L29/66 , H01L29/786
Abstract: Manufacturing methods for a low temperature poly-silicon array substrate and for a low temperature poly-silicon thin-film transistor are provided. The manufacturing method for the low temperature poly-silicon array substrate includes: providing a substrate; forming a poly-silicon semiconductor pattern on the substrate; a first channel region, a first source region and a first drain region being formed on a first portion of the poly-silicon semiconductor pattern that corresponds to the first thin-film transistor and a second thin-film transistor; forming a gate insulation layer; performing an activation treatment; forming a gate on the gate insulation layer after the activation treatment; forming an interlayer insulation layer between the gate insulation layer and the gate; performing a hydrogen treatment; forming a source/drain pattern on the interlayer insulation layer after the hydrogen treatment, and connecting the source/drain pattern to the source region and the drain region in the poly-silicon semiconductor pattern via a through hole.
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公开(公告)号：US20180069033A1
公开(公告)日：2018-03-08
申请号：US15115912
申请日：2016-06-17
Inventor： Chen Chen
IPC: H01L27/12 , G02F1/1368 , G02F1/1362
CPC classification number: H01L27/1262 , G02F1/136227 , G02F1/1368 , H01L27/1218 , H01L27/124 , H01L27/1248 , H01L29/78633
Abstract: The present invention provides a TFT array substrate structure and a manufacturing method thereof, in which an interlayer dielectric layer (3) having a three-layer structure comprising a lower silicon nitride layer (31), a silicon oxide layer (32), and an upper silicon nitride layer (33) is used, wherein the lower silicon nitride layer (31) contains hydrogen for supplying hydrogen ions for hydrogenation operations and the upper silicon nitride layer (33) improves an isolation and protection capability of the interlayer dielectric layer (3) against impurity ions, so as to, when compared to the prior art that involves an intermediate dielectric layer having a dual-layer structure comprising only a silicon oxide layer and a silicon nitride layer, improve the isolation and protection capability of the interlayer dielectric layer against impurity ions, without affecting an effect of hydrogenation, and eliminating potential risk of contamination by impurity ions, shortening hydrogenation time, and increasing throughput.
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公开(公告)号：US11522070B2
公开(公告)日：2022-12-06
申请号：US16968885
申请日：2018-10-08
Inventor： Chen Chen
IPC: H01L29/66 , H01L21/285 , H01L21/311 , H01L21/3213
Abstract: A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.
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公开(公告)号：US10700100B2
公开(公告)日：2020-06-30
申请号：US15740228
申请日：2017-10-20
Inventor： Chen Chen
IPC: G02F1/1368 , H01L27/12 , G02F1/1362
Abstract: A display panel, an array substrate and a method of forming the same are disclosed. The array substrate includes a plurality of pixel regions, each of the pixel regions includes a pixel electrode and at least one oxide film transistor. An input terminal of the pixel electrode is connected with an output terminal of the oxide film transistor, a control terminal of the oxide film transistor is connected with a scan line, an end of the scan line is connected with a drive circuit, and the oxide film transistor further includes a gate insulation layer disposed on a gate thereof. A thickness of the gate insulation layer is inversely proportional to a length of the scan line, which is connected with the corresponding gate, from a connection point with the drive circuit to a connection point with the gate.
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公开(公告)号：US10319748B2
公开(公告)日：2019-06-11
申请号：US15523001
申请日：2017-03-14
Inventor： Chen Chen
IPC: H01L27/12 , H01L27/02 , G02F1/1362 , G02F1/1335 , G02F1/1368
Abstract: Disclosed is a distribution of TFT components in the LTPS process. A pair of parallel data lines are arranged between an ith and (i+1)th rows of pixels. Each pair of data lines includes a first data line and a second data line. Two adjacent pixels of the ith row are respectively connected to the first data line and the second data line through corresponding U-shaped TFT components. Two pixels of the (n+1)th row corresponding to the two above adjacent pixels are respectively connected to the second data line and the first data line through corresponding U-shaped TFT components. The U-shaped TFT component of the pixel of the ith row and the U-shaped TFT component of the corresponding pixel of the (i+1)th row are disposed with openings thereof facing and staggered with each other. An aperture ratio of a product can be effectively increased by the staggered setting of the U-shaped TFT components. The use of such setting can realize dot inversion in the case of column inversion and reduce the power consumption of the product.
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