公开(公告)号：US20060208322A1

公开(公告)日：2006-09-21

申请号：US11413286

申请日：2006-04-28

申请人： Whonchee Lee ,  Scott Meikle ,  Guy Blalock

发明人： Whonchee Lee ,  Scott Meikle ,  Guy Blalock

IPC分类号： H01L21/20

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/32125 ,  H01L28/65 ,  H01L28/91

摘要： A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.

摘要翻译： 一种用于从微电子衬底去除相邻的导电和非导电材料的微电子衬底和方法。 在一个实施例中，微电子衬底包括具有设置在孔中的导电材料（例如铂）的孔的衬底材料（例如硼磷硅酸盐玻璃）和邻近导电的孔中的填充材料（例如磷硅玻璃） 材料。 填充材料可以具有约0.04GPa或更高的硬度，并且例如在从孔中去除填充材料之后，诸如电极的微电子结构可以设置在孔中。 孔的外部的导电和填充材料的部分可以通过化学机械抛光填充材料，将填充材料从导电材料向内凹陷，以及电化学机械抛光导电材料来去除。 硬填充材料可以抵抗导电颗粒的渗透，并且凹陷填充材料可以提供更全面地去除孔的外部的导电材料。

公开(公告)号：US20060199351A1

公开(公告)日：2006-09-07

申请号：US11413256

申请日：2006-04-28

申请人： Whonchee Lee ,  Scott Meikle ,  Guy Blalock

发明人： Whonchee Lee ,  Scott Meikle ,  Guy Blalock

IPC分类号： H01L21/20

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/32125 ,  H01L28/65 ,  H01L28/91

摘要： A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.

公开(公告)号：US20070040205A1

公开(公告)日：2007-02-22

申请号：US11209011

申请日：2005-08-22

申请人： Guy Blalock ,  Scott Meikle

发明人： Guy Blalock ,  Scott Meikle

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L28/65

摘要： The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

摘要翻译： 本教导涉及在基板上形成容器电容器结构的方法。 在一个实施例中，该方法包括蚀刻衬底中的凹槽，在衬底上沉积第一导电层以覆盖衬底和凹部，沉积填充层以覆盖第一导电层并填充凹槽，以及 蚀刻第一和第二导电层以便在凹陷内限定下电极。 所述方法还包括在所述下电极上形成覆盖层，以覆盖所述第一导电层和所述填充层，并且蚀刻所述衬底的至少一部分远离所述下电极，从而至少部分隔离所述下电极。 随后，电容器结构的其余部分可以通过在下电极上沉积电介质层并在电介质层上沉积第二导电层以形成上电极而形成。

公开(公告)号：US08106438B2

公开(公告)日：2012-01-31

申请号：US11209011

申请日：2005-08-22

申请人： Guy Blalock ,  Scott Meikle

发明人： Guy Blalock ,  Scott Meikle

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L28/65

摘要： The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

摘要翻译： 本教导涉及在基板上形成容器电容器结构的方法。 在一个实施例中，该方法包括蚀刻衬底中的凹槽，在衬底上沉积第一导电层以覆盖衬底和凹部，沉积填充层以覆盖第一导电层并填充凹槽，以及 蚀刻第一和第二导电层以便在凹陷内限定下电极。 所述方法还包括在所述下电极上形成覆盖层，以覆盖所述第一导电层和所述填充层，并且蚀刻所述衬底的至少一部分远离所述下电极，从而至少部分隔离所述下电极。 随后，电容器结构的其余部分可以通过在下电极上沉积电介质层并在电介质层上沉积第二导电层以形成上电极而形成。

公开(公告)号：US20100176083A1

公开(公告)日：2010-07-15

申请号：US12731049

申请日：2010-03-24

申请人： Whonchee Lee ,  Scott G. Meikle ,  Guy Blalock

发明人： Whonchee Lee ,  Scott G. Meikle ,  Guy Blalock

IPC分类号： H05K3/06 ,  H05K3/02

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/32125 ,  H01L28/65 ,  H01L28/91

摘要： A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.

摘要翻译： 一种用于从微电子衬底去除相邻的导电和非导电材料的微电子衬底和方法。 在一个实施例中，微电子衬底包括具有设置在孔中的导电材料（例如铂）的孔的衬底材料（例如硼磷硅酸盐玻璃）和邻近导电的孔中的填充材料（例如磷硅玻璃） 材料。 填充材料可以具有约0.04GPa或更高的硬度，并且例如在从孔中去除填充材料之后，诸如电极的微电子结构可以设置在孔中。 孔的外部的导电和填充材料的部分可以通过化学机械抛光填充材料，将填充材料从导电材料向内凹陷，以及电化学机械抛光导电材料来去除。 硬填充材料可以抵抗导电颗粒的渗透，并且凹陷填充材料可以提供更全面地去除孔的外部的导电材料。

公开(公告)号：US07078308B2

公开(公告)日：2006-07-18

申请号：US10230628

申请日：2002-08-29

申请人： Whonchee Lee ,  Scott G. Meikle ,  Guy Blalock

发明人： Whonchee Lee ,  Scott G. Meikle ,  Guy Blalock

IPC分类号： H01L21/8242

CPC分类号： H01L21/31053 ,  H01L21/3212 ,  H01L21/32125 ,  H01L28/65 ,  H01L28/91

摘要： A microelectronic substrate and method for removing adjacent conductive and nonconductive materials from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a substrate material (such as borophosphosilicate glass) having an aperture with a conductive material (such as platinum) disposed in the aperture and a fill material (such as phosphosilicate glass) in the aperture adjacent to the conductive material. The fill material can have a hardness of about 0.04 GPa or higher, and a microelectronics structure, such as an electrode, can be disposed in the aperture, for example, after removing the fill material from the aperture. Portions of the conductive and fill material external to the aperture can be removed by chemically-mechanically polishing the fill material, recessing the fill material inwardly from the conductive material, and electrochemically-mechanically polishing the conductive material. The hard fill material can resist penetration by conductive particles, and recessing the fill material can provide for more complete removal of the conductive material external to the aperture.

摘要翻译： 一种用于从微电子衬底去除相邻的导电和非导电材料的微电子衬底和方法。 在一个实施例中，微电子衬底包括具有设置在孔中的导电材料（例如铂）的孔的衬底材料（例如硼磷硅酸盐玻璃）和邻近导电的孔中的填充材料（例如磷硅玻璃） 材料。 填充材料可以具有约0.04GPa或更高的硬度，并且例如在从孔中去除填充材料之后，诸如电极的微电子结构可以设置在孔中。 孔的外部的导电和填充材料的部分可以通过化学机械抛光填充材料，将填充材料从导电材料向内凹陷，以及电化学机械抛光导电材料来去除。 硬填充材料可以抵抗导电颗粒的渗透，并且凹陷填充材料可以提供更全面地去除孔的外部的导电材料。

公开(公告)号：US07838381B2

公开(公告)日：2010-11-23

申请号：US11935968

申请日：2007-11-06

申请人： Guy Blalock ,  Scott Meikle

发明人： Guy Blalock ,  Scott Meikle

IPC分类号： H01L21/20

CPC分类号： H01L28/91 ,  H01L28/65

摘要： The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

摘要翻译： 本教导涉及在基板上形成容器电容器结构的方法。 在一个实施例中，该方法包括蚀刻衬底中的凹槽，在衬底上沉积第一导电层以覆盖衬底和凹部，沉积填充层以覆盖第一导电层并填充凹槽，以及 蚀刻第一和第二导电层以便在凹陷内限定下电极。 所述方法还包括在所述下电极上形成覆盖层，以覆盖所述第一导电层和所述填充层，并且蚀刻所述衬底的至少一部分远离所述下电极，从而至少部分隔离所述下电极。 随后，电容器结构的其余部分可以通过在下电极上沉积电介质层并在电介质层上沉积第二导电层以形成上电极而形成。

公开(公告)号：US20080057662A1

公开(公告)日：2008-03-06

申请号：US11935968

申请日：2007-11-06

申请人： Guy Blalock ,  Scott Meikle

发明人： Guy Blalock ,  Scott Meikle

IPC分类号： H01L29/94

CPC分类号： H01L28/91 ,  H01L28/65

摘要： The present teachings relate to a method of forming a container capacitor structure on a substrate. In one embodiment, the method comprises etching a recess in the substrate, depositing a first conductive layer on the substrate so as to overlie the substrate and the recess, depositing a filler layer so as to overlie the first conductive layer and fill the recess, and etching the first and second conductive layers so as to define a lower electrode within the recess. The method further comprises forming a cap layer on the lower electrode so as to overlie the first conductive layer and the filler layer and etching at least a portion of the substrate away from the lower electrode to thereby at least partially isolate the lower electrode. Subsequently, the remainder of the capacitor structure may be formed by depositing a dielectric layer on the lower electrode and depositing a second conductive layer on the dielectric layer so as to form an upper electrode.

摘要翻译： 本教导涉及在基板上形成容器电容器结构的方法。 在一个实施例中，该方法包括蚀刻衬底中的凹槽，在衬底上沉积第一导电层以覆盖衬底和凹部，沉积填充层以覆盖第一导电层并填充凹槽，以及 蚀刻第一和第二导电层以便在凹陷内限定下电极。 所述方法还包括在所述下电极上形成覆盖层，以覆盖所述第一导电层和所述填充层，并且蚀刻所述衬底的至少一部分远离所述下电极，从而至少部分隔离所述下电极。 随后，电容器结构的其余部分可以通过在下电极上沉积电介质层并在电介质层上沉积第二导电层以形成上电极而形成。

公开(公告)号：US20060249723A1

公开(公告)日：2006-11-09

申请号：US11484809

申请日：2006-07-11

申请人： Trung Doan ,  Guy Blalock ,  Mark Durcan ,  Scott Meikle

发明人： Trung Doan ,  Guy Blalock ,  Mark Durcan ,  Scott Meikle

IPC分类号： H01L47/00 ,  C03C15/00

CPC分类号： H01L21/31053

摘要： A method of manufacturing semiconductor devices using an improved chemical mechanical planarization process for the planarization of the surfaces of the wafer on which the semiconductor devices are formed. The improved chemical mechanical planarization process includes the formation of a flat planar surface from a deformable coating on the surface of the wafer filling in between the surface irregularities prior to the planarization of the surface through a chemical mechanical planarization process.

摘要翻译： 使用改进的化学机械平面化工艺制造半导体器件的方法，用于对其上形成半导体器件的晶片的表面进行平坦化。 改进的化学机械平面化处理包括从晶片表面上的可变形涂层形成平坦的平坦表面，其填充在通过化学机械平面化工艺在表面平坦化之前的表面凹凸之间。

公开(公告)号：US06274897B1

公开(公告)日：2001-08-14

申请号：US09339716

申请日：1999-06-24

申请人： Guy Blalock ,  Scott Meikle ,  Sung Kim ,  Kirk Prall

发明人： Guy Blalock ,  Scott Meikle ,  Sung Kim ,  Kirk Prall

IPC分类号： H01L27108

CPC分类号： H01L21/76838 ,  Y10S438/902 ,  Y10S438/959

摘要： A region is formed in a semiconductor substrate and extends beyond the substrate surface. First and second interconnects each having a predetermined thickness and a surface approximately parallel to the substrate surface are formed on the region. The first and second interconnects define a trench therebetween. A third interconnect is formed on the substrate. The thicknesses of the first and second interconnects are reduced a first amount to improve the aspect ratio of the trench, to improve the cross-sectional profile of the trench, or both. The thickness of the third strip is reduced a second amount. The second amount may be smaller than the first amount.

摘要翻译： 在半导体衬底中形成区域并延伸超过衬底表面。 在该区域上形成各自具有预定厚度的第一和第二互连以及大致平行于基板表面的表面。 第一和第二互连在其间限定沟槽。 在基板上形成第三互连。 第一和第二互连的厚度减小了第一量以改善沟槽的纵横比，以改善沟槽的横截面轮廓或两者。 第三条带的厚度减少第二量。 第二量可以小于第一量。