公开(公告)号：US20100177106A1

公开(公告)日：2010-07-15

申请号：US12686508

申请日：2010-01-13

Applicant: Wan-jung Kim ,  Chan-ho Lee ,  Tae-hyoung Kim

Inventor： Wan-jung Kim ,  Chan-ho Lee ,  Tae-hyoung Kim

IPC: G09G5/39 ,  G09G5/00

CPC classification number: G09G5/001 ,  G09G3/20 ,  G09G5/39

Abstract: An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit. The arbitration circuit includes a latch unit having a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation, and a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation.

Abstract translation: 仲裁电路，用于仲裁读/写命令和扫描命令之间的问题以及包括仲裁电路的显示驱动器集成电路。 仲裁电路包括一个锁存单元，该锁存单元具有锁存和输出与扫描命令有关的第一信号的第一锁存电路和锁存并输出与读/写命令相关的第二信号的第二锁存电路，其中锁存单元复位输出 的第一锁存电路和/或第二锁存电路响应于与存储器操作相关的就绪信号，以及维持单元，用于接收第一锁存电路和第二锁存电路的输出，以产生第一内部信号以激活 扫描操作和第二内部信号以激活读/写操作，保持第一内部信号和第二内部信号，并且通过改变第一内部信号或第二内部信号中的至少一个的状态来选择性地启动第一内部信号或第二内部信号 第一内部信号和第二内部信号响应复位操作。

公开(公告)号：US08711162B2

公开(公告)日：2014-04-29

申请号：US12686508

申请日：2010-01-13

Applicant: Wan-jung Kim ,  Chan-ho Lee ,  Tae-hyoung Kim

Inventor： Wan-jung Kim ,  Chan-ho Lee ,  Tae-hyoung Kim

IPC: G09G5/39 ,  G06F15/167

CPC classification number: G09G5/001 ,  G09G3/20 ,  G09G5/39

Abstract: An arbitration circuit to arbitrate an issue between a read/write command and a scan command and a display driver integrated circuit including the arbitration circuit. The arbitration circuit includes a latch unit having a first latch circuit that latches and outputs a first signal related to a scan command and a second latch circuit that latches and outputs a second signal related to a read/write command, wherein the latch unit resets outputs of the first latch circuit and/or the second latch circuit in response to a ready signal related to a memory operation, and a maintaining unit to receive outputs of the first latch circuit and the second latch circuit, to generate a first internal signal to activate a scanning operation and a second internal signal to activate a reading/writing operation, maintain the first internal signal and the second internal signal, and to selectively activate the first internal signal or the second internal signal by changing the state of at least one of the first internal signal and second internal signal in response to the reset operation.

Abstract translation: 仲裁电路，用于仲裁读/写命令和扫描命令之间的问题以及包括仲裁电路的显示驱动器集成电路。 仲裁电路包括一个锁存单元，该锁存单元具有锁存和输出与扫描命令有关的第一信号的第一锁存电路和锁存并输出与读/写命令相关的第二信号的第二锁存电路，其中锁存单元复位输出 的第一锁存电路和/或第二锁存电路响应于与存储器操作相关的就绪信号，以及维持单元，用于接收第一锁存电路和第二锁存电路的输出，以产生第一内部信号以激活 扫描操作和第二内部信号以激活读/写操作，保持第一内部信号和第二内部信号，并且通过改变第一内部信号或第二内部信号中的至少一个的状态来选择性地启动第一内部信号或第二内部信号 第一内部信号和第二内部信号响应复位操作。

公开(公告)号：US07057420B2

公开(公告)日：2006-06-06

申请号：US10873943

申请日：2004-06-22

Applicant: Tae-joong Song ,  Tae-hyoung Kim

Inventor： Tae-joong Song ,  Tae-hyoung Kim

IPC: G11C7/00

CPC classification number: G11C7/14 ,  G11C7/06 ,  G11C2207/065

Abstract: A semiconductor device having a sense amplifier driver with a capacitor affected by off current is provided. The sense amplifier driver, which receives a clock signal and generates a sense amplifier enable signal by buffering the clock signal, includes a plurality of inverters connected in series and at least one capacitor. A PMOS transistor of at least a first inverter of the plurality of inverters is connected between a dummy bit line, in which voltage drop by the off current is generated, and the output terminal of the first inverter and the at least one capacitor is connected between the dummy bit line and the output terminal of a second inverter which inverts an output signal of the first inverter. Therefore, the capacitance of the at least one capacitor is determined by voltage of the dummy bit line. Therefore, since the voltage drop of the dummy bit line is larger when the magnitude of the off current is larger, the capacitance of the at least one capacitor is larger. Therefore, active timing of the sense amplifier enable signal is determined according to the capacitance of the capacitor.

Abstract translation: 提供一种具有感测放大器驱动器的半导体器件，其具有受截止电流影响的电容器。 通过缓冲时钟信号接收时钟信号并产生读出放大器使能信号的读出放大器驱动器包括串联连接的多个反相器和至少一个电容器。 多个反相器的至少第一反相器的PMOS晶体管连接在其中产生通过截止电流的电压降与第一反相器的输出端之间的虚拟位线和至少一个电容器之间连接在 第二反相器的虚拟位线和输出端反转第一反相器的输出信号。 因此，至少一个电容器的电容由虚拟位线的电压决定。 因此，由于当截止电流的大小较大时，虚拟位线的电压降较大，所以至少一个电容器的电容较大。 因此，根据电容器的电容来确定读出放大器使能信号的有效定时。

公开(公告)号：US20050144890A1

公开(公告)日：2005-07-07

申请号：US10814642

申请日：2004-04-01

Applicant: Won-keun Kim ,  Moon-pal Kim ,  Hyun-kee Shin ,  Seoung-kyoo Park ,  Tae-hyoung Kim ,  Young-ho Son

Inventor： Won-keun Kim ,  Moon-pal Kim ,  Hyun-kee Shin ,  Seoung-kyoo Park ,  Tae-hyoung Kim ,  Young-ho Son

IPC: E01D1/00 ,  E01D2/00 ,  E01D2/02 ,  E01D21/00 ,  E01D101/24 ,  E04B1/21 ,  E04B1/58 ,  E04B1/00 ,  E04C5/00

CPC classification number: E01D2/02 ,  E01D2/00 ,  E01D2101/285

Abstract: A structure and method of connecting a plurality of PSC-I beams (PSC-I beams) to each other using steel brackets. The beam connecting structure, each having a sheath pipe therein, includes an end plate which is mounted on each of both ends of each of the PSC-I beams, with a through hole provided on an upper portion of the end plate to correspond to the sheath pipe embedded in each of the PSC-I beams; a steel bracket integrally which is provided on the end plate to be perpendicular to the end plate; a bracket coupling plate to integrally couple the aligned steel brackets to each other; a bottom connecting plate which is provided on lower ends of the aligned steel brackets to connect the steel brackets to each other; a connecting sheath pipe which is provided between the PSC-I beams so that both ends of the connecting sheath pipe are respectively inserted into the through holes of the neighboring end plates of the PSC-I beams while the PSC-I beams are arranged linearly; a prestress strand which is inserted in the sheath pipes of the PSC-I beams and the connecting sheath pipe; and a concrete part which is filled in a space between the PSC-I beams to embed the aligned steel brackets, the bracket coupling plate and the connecting sheath pipe in the concrete part.

Abstract translation: 使用钢支架将多个PSC-I梁（PSC-I梁）彼此连接的结构和方法。 每个在其中具有护套管的梁连接结构包括安装在每个PSC-I梁的两端中的端板，其中通孔设置在端板的上部，以对应于 护套管嵌入每个PSC-I梁; 整体地设置在所述端板上以垂直于所述端板的钢托架; 托架联接板，用于将对准的钢支架彼此一体地联接; 底部连接板，其设置在对准的钢支架的下端，以将钢支架相互连接; 设置在PSC-I梁之间的连接护套管，使得连接护套管的两端分别插入到PSC-I梁的相邻端板的通孔中，同时PSC-I梁被线性布置; 插入在PSC-I梁的护套管和连接护套管中的预应力绳; 以及填充在PSC-I梁之间的空间中的混凝土部件，以将对准的钢托架，托架联接板和连接护套管嵌入混凝土部件中。

公开(公告)号：US20050104627A1

公开(公告)日：2005-05-19

申请号：US10873943

申请日：2004-06-22

Applicant: Tae-joong Song ,  Tae-hyoung Kim

Inventor： Tae-joong Song ,  Tae-hyoung Kim

IPC: G11C11/419 ,  G11C7/06 ,  G11C7/14 ,  G11C11/409 ,  G11C7/00

CPC classification number: G11C7/14 ,  G11C7/06 ,  G11C2207/065

Abstract: A semiconductor device having a sense amplifier driver with a capacitor affected by off current is provided. The sense amplifier driver, which receives a clock signal and generates a sense amplifier enable signal by buffering the clock signal, includes a plurality of inverters connected in series and at least one capacitor. A PMOS transistor of at least a first inverter of the plurality of inverters is connected between a dummy bit line, in which voltage drop by the off current is generated, and the output terminal of the first inverter and the at least one capacitor is connected between the dummy bit line and the output terminal of a second inverter which inverts an output signal of the first inverter. Therefore, the capacitance of the at least one capacitor is determined by voltage of the dummy bit line. Therefore, since the voltage drop of the dummy bit line is larger when the magnitude of the off current is larger, the capacitance of the at least one capacitor is larger. Therefore, active timing of the sense amplifier enable signal is determined according to the capacitance of the capacitor.

Abstract translation: 提供一种具有感测放大器驱动器的半导体器件，其具有受截止电流影响的电容器。 通过缓冲时钟信号接收时钟信号并产生读出放大器使能信号的读出放大器驱动器包括串联连接的多个反相器和至少一个电容器。 多个反相器的至少第一反相器的PMOS晶体管连接在其中产生通过截止电流的电压降与第一反相器的输出端之间的虚拟位线和至少一个电容器之间连接在 第二反相器的虚拟位线和输出端反转第一反相器的输出信号。 因此，至少一个电容器的电容由虚拟位线的电压决定。 因此，由于当截止电流的大小较大时，虚拟位线的电压降较大，所以至少一个电容器的电容较大。 因此，根据电容器的电容来确定读出放大器使能信号的有效定时。