-
1.发明申请公开(公告)号：US20200111818A1
公开(公告)日：2020-04-09
申请号：US16308824
申请日：2018-11-20
Inventor： Chen CHEN
IPC: H01L27/12
Abstract: The present disclosure proposes a method of producing an LTPS TFT array substrate. The method is about stacking of a gate insulating layer and an interlayer insulating layer for providing conditions for formation of a gate trench. In addition, stacking of the gate insulating layer and the interlayer insulating layer is produced with some blocks of forming a hole on the gate insulating layer and the interlayer insulating layer to form a hole pattern, filling the gate trench, and producing gate lines. In this way, the formation of the gate lines and the formation of the hole pattern on the gate insulating layer and the interlayer insulating layer are done using the same mask. The method of the present disclosure reduces the number of masks required compared with the method of the related art, thereby reducing the production costs.
-
公开(公告)号：US20200027899A1
公开(公告)日：2020-01-23
申请号：US15744298
申请日：2017-10-20
Inventor： Chen CHEN
IPC: H01L27/12 , G02F1/1337 , G02F1/1368 , G02F1/1362
Abstract: The present disclosure provides an array substrate, a display panel and a manufacturing method of the array substrate, and the array substrate comprises a gate line, a thin film transistor (TFT), a passivation layer and a pixel electrode; wherein the gate line is electrically connected to a gate electrode of the thin film transistor, the pixel electrode is electrically connected to a drain electrode of the thin film transistor, the passivation layer is located between a layer where the thin film transistor is located and a layer where the pixel electrode is located, the passivation layer has a thickness gradually changed along an extending direction of the gate line. The present disclosure can improve the uniformity of displayed images by the above array substrate.
-
公开(公告)号：US20190267408A1
公开(公告)日：2019-08-29
申请号：US16044948
申请日：2018-07-25
Inventor： Chen CHEN
IPC: H01L27/12 , H01L29/786 , H01L29/417
Abstract: The present invention discloses an array substrate for forming a display panel, comprising: a substrate; a thin-film transistor disposed on the substrate, the thin-film transistor comprising a drain electrode; a planarization layer disposed on the thin-film transistor, the planarization layer being provided with a first via hole for exposing the drain electrode; a pixel electrode layer disposed on the surface of the planarization layer away from the substrate, the pixel electrode layer covering the first via hole and being in contact with the drain electrode; and a photoresist layer covering the pixel electrode layer, and the photoresist layer filling the first via hole which is covered with the pixel electrode layer. The present invention solves the issues caused by the height difference in products.
-
公开(公告)号：US20210050432A1
公开(公告)日：2021-02-18
申请号：US16968885
申请日：2018-10-08
Inventor： Chen CHEN
IPC: H01L29/66 , H01L21/311 , H01L21/285 , H01L21/3213
Abstract: A manufacturing method of a low temperature poly-silicon (LTPS) array substrate is described. The LTPS array substrate includes a metal light-shielding layer, a buffer layer, a polycrystalline silicon layer, a gate insulating and interlayer insulating layer, a gate line layer, and a source and drain electrode layer. The method adopts a one-time chemical vapor deposition process to form a gate insulator and interlayer insulating layer. A gate line trench is formed in the gate insulating layer and the interlayer insulating layer, thereby reducing the thickness of the LTPS array substrate film layer and the process steps.
-
-
-
Search Results
4
records
(took 0.019 seconds)
