公开(公告)号：US07830887B2

公开(公告)日：2010-11-09

申请号：US11082975

申请日：2005-03-18

Applicant: Vamsi Tatapudi ,  Nithyananda Miyar

Inventor： Vamsi Tatapudi ,  Nithyananda Miyar

IPC: H04L12/28

CPC classification number: H04L47/6285 ,  H04L47/50

Abstract: A switching chip for performing switching and other functions on packets transmitted through the switching chip. The switching chip includes a memory management unit that identifies a class of service to which each packet belongs, wherein upon processing the packet. The memory management unit transmits the packet to a CPU through a CPU processing module. The switching chip also includes a CPU processing module that includes a class of service bitmap that is associated with a plurality of channels. Each of the plurality of channels is further associated with at least one class of service, includes a per channel bit and is assigned a predefined priority level. Upon receiving packets from the memory management unit, the CPU processing module is configured to sort the packets according to the class of service to which the packet belongs and store each packet in an associated one of the plurality of channels. The CPU processing module is also configured to use the per channel bit to determine how to process packets in each for the plurality of channels for which there is no available CPU buffer. When there is no available CPU buffer for one of the plurality of channels, the CPU processing module is configured to set an appropriate bit in the class of service bitmap and transmits the class of service bitmap to the memory management unit.

Abstract translation: 一种用于对通过交换芯片发送的分组执行切换和其他功能的交换芯片。 切换芯片包括识别每个分组所属的一类服务的存储器管理单元，其中处理分组时。 存储器管理单元通过CPU处理模块将数据包发送到CPU。 切换芯片还包括CPU处理模块，其包括与多个通道相关联的一类服务位图。 多个通道中的每一个进一步与至少一类服务相关联，包括每通道位并被分配预定义的优先级。 在从存储器管理单元接收到分组时，CPU处理模块被配置为根据分组所属的服务类别对分组进行分类，并将每个分组存储在多个信道中的相关联的一个信道中。 CPU处理模块还被配置为使用每个通道位来确定如何处理针对不存在可用CPU缓冲器的多个通道的分组。 当多个通道之一没有可用的CPU缓冲器时，CPU处理模块被配置为在服务类位图中设置适当的位，并将服务类位图发送到存储器管理单元。

公开(公告)号：US20060114937A1

公开(公告)日：2006-06-01

申请号：US11082975

申请日：2005-03-18

Applicant: Vamsi Tatapudi ,  Nithyananda Miyar

Inventor： Vamsi Tatapudi ,  Nithyananda Miyar

IPC: H04L12/26 ,  H04J3/16 ,  G01R31/08 ,  H04L1/00 ,  H04J3/22

CPC classification number: H04L47/6285 ,  H04L47/50

Abstract: A switching chip for performing switching and other functions on packets transmitted through the switching chip. The switching chip includes a memory management unit that identifies a class of service to which each packet belongs, wherein upon processing the packet. The memory management unit transmits the packet to a CPU through a CPU processing module. The switching chip also includes a CPU processing module that includes a class of service bitmap that is associated with a plurality of channels. Each of the plurality of channels is further associated with at least one class of service, includes a per channel bit and is assigned a predefined priority level. Upon receiving packets from the memory management unit, the CPU processing module is configured to sort the packets according to the class of service to which the packet belongs and store each packet in an associated one of the plurality of channels. The CPU processing module is also configured to use the per channel bit to determine how to process packets in each for the plurality of channels for which there is no available CPU buffer. When there is no available CPU buffer for one of the plurality of channels, the CPU processing module is configured to set an appropriate bit in the class of service bitmap and transmits the class of service bitmap to the memory management unit.

Abstract translation: 一种用于对通过交换芯片发送的分组执行切换和其他功能的交换芯片。 切换芯片包括识别每个分组所属的一类服务的存储器管理单元，其中处理分组时。 存储器管理单元通过CPU处理模块将数据包发送到CPU。 切换芯片还包括CPU处理模块，其包括与多个通道相关联的一类服务位图。 多个通道中的每一个进一步与至少一类服务相关联，包括每通道位并被分配预定义的优先级。 在从存储器管理单元接收到分组时，CPU处理模块被配置为根据分组所属的服务类别对分组进行分类，并将每个分组存储在多个信道中的相关联的一个信道中。 CPU处理模块还被配置为使用每个通道位来确定如何处理针对不存在可用CPU缓冲器的多个通道的分组。 当多个通道之一没有可用的CPU缓冲器时，CPU处理模块被配置为在服务类位图中设置适当的位，并将服务类位图发送到存储器管理单元。