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公开(公告)号：US20200294971A1
公开(公告)日：2020-09-17
申请号：US16561658
申请日：2019-09-05
IPC分类号： H01L25/065 , H01L25/18 , H01L23/00 , H01L25/00
摘要： In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.
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公开(公告)号：US10249531B1
公开(公告)日：2019-04-02
申请号：US15892536
申请日：2018-02-09
IPC分类号： C23C18/18 , H01L21/768 , H01L23/00 , C23C18/31 , C23C18/16
摘要： A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
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公开(公告)号：US20190088872A1
公开(公告)日：2019-03-21
申请号：US15892564
申请日：2018-02-09
发明人： Yusuke Tanaka , Atsushi Hieno
摘要： A storage device according to an embodiment includes a first conductive layer, a second conductive layer, and a resistance change layer. The resistance change layer is positioned between the first conductive layer and the second conductive layer. The resistance change layer including an organic compound. The organic compound has at least one first functional group selected from the group consisting of an amino group, a thiol group, a carboxy group, and an azide group, and the organic compound has one or less aromatic rings.
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公开(公告)号：US11152334B2
公开(公告)日：2021-10-19
申请号：US16561658
申请日：2019-09-05
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
摘要： In one embodiment, a semiconductor device includes a first chip that includes a first interconnect layer, a first insulator provided on the first interconnect layer, a first metal portion provided on the first interconnect layer and provided in the first insulator and including at least one of palladium, platinum and gold, and a second interconnect layer provided on the first metal portion and provided in the first insulator. The device further includes a second chip that includes a second insulator provided on the first insulator, and a third interconnect layer provided in the second insulator and provided on the second interconnect layer.
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公开(公告)号：US20190088539A1
公开(公告)日：2019-03-21
申请号：US15892536
申请日：2018-02-09
IPC分类号： H01L21/768 , H01L23/00 , C23C18/31 , C23C18/16 , C23C18/18
摘要： A method for forming a metal wiring according to embodiments includes forming a first insulating layer on a substrate; forming a catalyst adsorption layer by bringing a surface of the first insulating layer into contact with a solution containing a compound having a triazine skeleton, a first functional group of one of a silanol group and an alkoxysilyl group, and a second functional group of at least one selected from the group consisting of an amino group, a thiol group, a carboxyl group, and an azide group; forming a second insulating layer different from the first insulating layer on the catalyst adsorption layer; patterning the second insulating layer to form a mask pattern; etching the first insulating layer by a wet etching method; selectively forming a catalyst layer; and forming a metal layer on the catalyst layer by an electroless plating method.
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