公开(公告)号：US06483134B1

公开(公告)日：2002-11-19

申请号：US08656494

申请日：1996-05-31

申请人： Todd R. Weatherford ,  Dale P. McMorrow ,  Walter R. Curtice

发明人： Todd R. Weatherford ,  Dale P. McMorrow ,  Walter R. Curtice

IPC分类号： H01L29812

CPC分类号： H01L29/207 ,  H01L29/32 ,  H01L29/802 ,  H01L29/812

摘要： The present invention is an electronic structure having a buffer layer with a short average carrier lifetime, at least about 1000 Å thick with an upper face, and an integrated circuit disposed over the upper face of the buffer layer, where this integrated circuit would otherwise be susceptible to soft errors, due to its configuration, its clock speed, its use environment, or a combination of these factors. In a preferred embodiment, the preferably high recombination rate buffer layer is an LT GaAs or GaAs:Er buffer layer.

摘要翻译： 本发明是一种电子结构，其具有平均载流子寿命短的平板载流子缓冲层，具有上表面的至少约为1000的厚度，以及设置在缓冲层的上表面上的集成电路， 由于其配置，其时钟速度，其使用环境或这些因素的组合，易受软错误的影响。 在优选实施例中，优选高复合速率缓冲层是LT GaAs或GaAs：Er缓冲层。