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    Array—type computer processor with reduced instruction storage
    2.
    发明授权
    Array—type computer processor with reduced instruction storage 有权
    阵列式计算机处理器，减少指令存储

    公开(公告)号：US07650484B2

    公开(公告)日：2010-01-19

    申请号：US11049305

    申请日：2005-02-03

    申请人： Takeshi Inuo ,  Nobuki Kajihara ,  Takao Toi ,  Tooru Awashima ,  Hirokazu Kami ,  Taro Fujii ,  Kenichiro Anjo ,  Kouichiro Furuta ,  Masato Motomura

    发明人： Takeshi Inuo ,  Nobuki Kajihara ,  Takao Toi ,  Tooru Awashima ,  Hirokazu Kami ,  Taro Fujii ,  Kenichiro Anjo ,  Kouichiro Furuta ,  Masato Motomura

    IPC分类号： G06F7/00

    CPC分类号： G06F15/8023 ,  G06F9/30036 ,  G06F9/3879 ,  G06F9/3887

    摘要： An array-type computer processor including a data path unit communicating with a state control unit obtains data of a predetermined number of cooperative partial instruction codes, and operates with temporarily holding only a predetermined number of data-obtained instruction codes comprising cooperative partial instruction codes corresponding to contexts and operation states for the data path unit and the state control unit, respectively, from an external program memory which stores data of a computer program. Every time the operations with the temporarily-held instruction codes, including the corresponding cooperative partial instruction codes, are complete, in accordance with event data entered in the state control unit, the subsequent instruction codes are data obtained as cooperative partial instruction codes respectively corresponding to contexts and operating states, so that the operation according to a computer program can be performed even if the data volume of the computer program is over the storage capacity of the data path unit and the state control unit.

    摘要翻译： 包括与状态控制单元通信的数据路径单元的阵列式计算机处理器获得预定数量的协同部分指令代码的数据，并且暂时保持包含协调部分指令代码对应的预定数量的数据获取指令代码 分别用于存储计算机程序的数据的外部程序存储器的数据路径单元和状态控制单元的上下文和操作状态。 每当具有临时保持的指令代码的操作（包括相应的协同部分指令代码）完成时，根据输入到状态控制单元中的事件数据，后续指令代码是分别对应于 上下文和操作状态，使得即使计算机程序的数据量超过数据路径单元和状态控制单元的存储容量，也可以执行根据计算机程序的操作。

    Array-type computer processor
    3.
    发明授权
    Array-type computer processor 有权
    阵列型计算机处理器

    公开(公告)号：US07287146B2

    公开(公告)日：2007-10-23

    申请号：US11048071

    申请日：2005-02-02

    申请人： Takeshi Inuo ,  Nobuki Kajihara ,  Takao Toi ,  Tooru Awashima ,  Hirokazu Kami ,  Taro Fujii ,  Kenichiro Anjo ,  Kouichiro Furuta ,  Masato Motomura

    发明人： Takeshi Inuo ,  Nobuki Kajihara ,  Takao Toi ,  Tooru Awashima ,  Hirokazu Kami ,  Taro Fujii ,  Kenichiro Anjo ,  Kouichiro Furuta ,  Masato Motomura

    IPC分类号： G06F7/00

    CPC分类号： G06F15/8023 ,  G06F15/7867

    摘要： An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.

    摘要翻译： 当输入用于任务切换的事件数据时，阵列式计算机处理器停止，多个计算机程序保持状态控制单元和数据路径单元。 阵列型计算机处理器在停止时获取状态控制单元的操作状态和数据路径单元的处理数据，并且为多个计算机程序中的每一个暂时保存它们。 完成后，阵列型计算机处理器读取任何其他计算机程序的操作状态和处理数据，并将其设置在状态控制单元和数据路径单元中。 完成后，阵列型计算机处理器向状态控制单元输出用于开始操作的事件数据。 状态控制单元然后开始顺序地传送操作状态，从而使得可以以分时方式执行根据多个计算机程序的处理操作。

    Array-type computer processor
    4.
    发明申请
    Array-type computer processor 有权
    阵列型计算机处理器

    公开(公告)号：US20050172102A1

    公开(公告)日：2005-08-04

    申请号：US11048071

    申请日：2005-02-02

    申请人： Takeshi Inuo ,  Nobuki Kajihara ,  Takao Toi ,  Tooru Awashima ,  Hirokazu Kami ,  Taro Fujii ,  Kenichiro Anjo ,  Kouichiro Furuta ,  Masato Motomura

    发明人： Takeshi Inuo ,  Nobuki Kajihara ,  Takao Toi ,  Tooru Awashima ,  Hirokazu Kami ,  Taro Fujii ,  Kenichiro Anjo ,  Kouichiro Furuta ,  Masato Motomura

    IPC分类号： G06F9/46 ,  G06F15/00 ,  G06F15/80

    CPC分类号： G06F15/8023 ,  G06F15/7867

    摘要： An array-type computer processor stops, with a plurality of computer programs held, a state control unit and a data-path unit, upon input of event data for task switching. The array-type computer processor obtains the operation state of the state control unit and the processed data of the data-path unit when stopped, and temporarily holds them for each of a plurality of the computer programs. Upon completion of this, the array-type computer processor reads the operation state and processed data of any other computer program and sets them in the state control unit and data-path unit. Upon completion of this, the array-type computer processor outputs to the state control unit the event data for starting the operation. The state control unit then starts to sequentially transfer the operation state, thereby making it possible to perform the process operations according to a plurality of computer programs in a time-sharing manner.

    摘要翻译： 当输入用于任务切换的事件数据时，阵列式计算机处理器停止，多个计算机程序保持状态控制单元和数据路径单元。 阵列型计算机处理器在停止时获取状态控制单元的操作状态和数据路径单元的处理数据，并且为多个计算机程序中的每一个暂时保存它们。 完成后，阵列型计算机处理器读取任何其他计算机程序的操作状态和处理数据，并将其设置在状态控制单元和数据路径单元中。 完成后，阵列型计算机处理器向状态控制单元输出用于开始操作的事件数据。 状态控制单元然后开始顺序地传送操作状态，从而使得可以以分时方式执行根据多个计算机程序的处理操作。

    Data processing system for debugging utilizing halts in a parallel device
    7.
    发明授权
    Data processing system for debugging utilizing halts in a parallel device 有权
    数据处理系统，用于并行设备中的停止调试

    公开(公告)号：US07647485B2

    公开(公告)日：2010-01-12

    申请号：US10927377

    申请日：2004-08-27

    申请人： Hirokazu Kami ,  Takao Toi ,  Toru Awashima ,  Kenichiro Anjo ,  Koichiro Furuta ,  Taro Fujii ,  Masato Motomura

    发明人： Hirokazu Kami ,  Takao Toi ,  Toru Awashima ,  Kenichiro Anjo ,  Koichiro Furuta ,  Taro Fujii ,  Masato Motomura

    IPC分类号： G06F9/00

    CPC分类号： G06F11/3624 ,  G06F11/3632

    摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

    摘要翻译： 一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起 所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

    Data processing system
    8.
    发明申请
    Data processing system 有权
    数据处理系统

    公开(公告)号：US20050050522A1

    公开(公告)日：2005-03-03

    申请号：US10927377

    申请日：2004-08-27

    申请人： Hirokazu Kami ,  Takao Toi ,  Toru Awashima ,  Kenichiro Anjo ,  Koichiro Furuta ,  Taro Fujii ,  Masato Motomura

    发明人： Hirokazu Kami ,  Takao Toi ,  Toru Awashima ,  Kenichiro Anjo ,  Koichiro Furuta ,  Taro Fujii ,  Masato Motomura

    IPC分类号： G06F11/28 ,  G06F15/76 ,  G06F15/80

    CPC分类号： G06F11/3624 ,  G06F11/3632

    摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

    摘要翻译： 一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起 所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

    Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix
    9.
    发明授权
    Array-type processor having state control units controlling a plurality of processor elements arranged in a matrix 有权
    具有状态控制单元的阵列式处理器，其控制以矩阵形式布置的多个处理器元件

    公开(公告)号：US07523292B2

    公开(公告)日：2009-04-21

    申请号：US10682830

    申请日：2003-10-10

    申请人： Taro Fujii ,  Koichiro Furuta ,  Masato Motomura ,  Kenichiro Anjo ,  Yoshikazu Yabe ,  Toru Awashima ,  Takao Toi ,  Noritsugu Nakamura

    发明人： Taro Fujii ,  Koichiro Furuta ,  Masato Motomura ,  Kenichiro Anjo ,  Yoshikazu Yabe ,  Toru Awashima ,  Takao Toi ,  Noritsugu Nakamura

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/8007

    摘要： A multiplicity of processor elements, which both individually execute data processing in accordance with instruction codes that have been set as data and for which mutual connection relations are switch-controlled, are arranged in matrix form, and the instruction codes of this multiplicity of processor elements are successively switched by a state control unit. The state control units are composed of a plurality of units that intercommunicate to realize linked operation, and the multiplicity of processor elements is divided into a number of element areas that corresponds to the number of state control units. The plurality of state control units are arranged for each of the plurality of element areas and are connected to the processor elements, whereby the plurality of state control units can individually control a plurality of small-scale state transitions, or the plurality of state control units can cooperate to control a single large-scale state transition.

    摘要翻译： 多个处理器元件分别按照已经被设置为数据并且相互连接关系被切换控制的指令代码单独执行数据处理，以矩阵形式排列，并且该多个处理器元件的指令代码 被状态控制单元依次切换。 状态控制单元由多个单元组成，这些单元相互通信以实现链接操作，并且多个处理器元件被分成与状态控制单元数量相对应的多个元件区域。 多个状态控制单元被布置用于多个元件区域中的每一个，并且连接到处理器元件，由此多个状态控制单元可以单独地控制多个小规模状态转换，或者多个状态控制单元 可以合作控制单一的大规模国家转型。

    Array-type processor having plural processor elements controlled by a state control unit
    10.
    发明授权
    Array-type processor having plural processor elements controlled by a state control unit 有权
    具有由状态控制单元控制的多个处理器单元的阵列型处理器

    公开(公告)号：US08151089B2

    公开(公告)日：2012-04-03

    申请号：US10694822

    申请日：2003-10-29

    申请人： Taro Fujii ,  Koichiro Furuta ,  Masato Motomura ,  Kenichiro Anjo ,  Yoshikazu Yabe ,  Toru Awashima ,  Takao Toi ,  Noritsugu Nakamura

    发明人： Taro Fujii ,  Koichiro Furuta ,  Masato Motomura ,  Kenichiro Anjo ,  Yoshikazu Yabe ,  Toru Awashima ,  Takao Toi ,  Noritsugu Nakamura

    IPC分类号： G06F15/00 ,  G06F15/76

    CPC分类号： G06F15/8007

    摘要： A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

    摘要翻译： 排列成行和列的多个处理器元件根据单独设置为数据并提供事件数据作为输出的指令代码单独执行数据处理。 状态控制单元由多个单元组成，多个单元根据计算机程序和事件数据连续地切换多个处理器单元的指令代码，这些状态控制单元相互通信以根据需要实现链接操作。 事件分配装置将事件数据分配给相互通信的多个状态控制单元，以实现链接操作，由此多个状态控制单元可以实现链接操作以控制大规模状态转换。