公开(公告)号：US07647485B2

公开(公告)日：2010-01-12

申请号：US10927377

申请日：2004-08-27

申请人： Hirokazu Kami ,  Takao Toi ,  Toru Awashima ,  Kenichiro Anjo ,  Koichiro Furuta ,  Taro Fujii ,  Masato Motomura

发明人： Hirokazu Kami ,  Takao Toi ,  Toru Awashima ,  Kenichiro Anjo ,  Koichiro Furuta ,  Taro Fujii ,  Masato Motomura

IPC分类号： G06F9/00

CPC分类号： G06F11/3624 ,  G06F11/3632

摘要： A data processing device for debugging code for a parallel arithmetic device that includes a plurality of data processing circuits arranged in a matrix and that causes, for each operating cycle, successive transitions of operation states in accordance with object code includes: operation execution means for causing the parallel arithmetic device to execute state transitions by means of the object code; device halt means for temporarily halting the state transitions for each operating cycle; a result output means for reading and supplying as output at least a portion of held data, connection relations, and operation commands of the plurality of data processing circuits of the halted parallel arithmetic device; a resume input means for receiving as input a resume command of the state transitions; and an operation resumption means for causing the operation execution means to resume the state transitions upon input of a resume command.

摘要翻译： 一种用于并行运算装置调试码的数据处理装置，包括以矩阵形式布置的多个数据处理电路，并且根据目标代码使每个操作周期的操作状态的连续转换包括：操作执行装置，用于引起 所述并行算术装置通过所述目标代码执行状态转换; 设备停止装置，用于暂时停止每个操作周期的状态转换; 结果输出装置，用于读取和提供停止的并行运算装置的多个数据处理电路的保持数据，连接关系和操作命令的至少一部分的输出; 恢复输入装置，用于接收状态转换的恢复命令作为输入; 以及操作恢复装置，用于使得操作执行装置在输入恢复命令时恢复状态转换。

公开(公告)号：US20080040700A1

公开(公告)日：2008-02-14

申请号：US11727948

申请日：2007-03-29

申请人： Yoshinosuke Katoh ,  Toru Awashima ,  Noritsugu Nakamura ,  Hirokazu Kami ,  Takao Toi

发明人： Yoshinosuke Katoh ,  Toru Awashima ,  Noritsugu Nakamura ,  Hirokazu Kami ,  Takao Toi

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F17/5045

摘要： The liveness information that is obtained from behavioral synthesis and that shows the periods during which variables described in a behavioral level description have valid values is used for processing at a logic synthesizing stage, placement and routing stage, debugging stage, writing stage of circuit information to a reconfigurable device, or the like, so as to use storage elements that are to be allocated to the variables described in the behavioral level description in common and to achieve optimization such as minimizing data paths and the like. Also in a debugger and in a writing device for writing circuit information, the aforementioned liveness information is used to execute a task of not displaying invalid variables, a task of reducing the amount of information to be saved to an external memory, etc.

摘要翻译： 从行为综合获得的活动信息，并且显示了在行为级别描述中描述的变量具有有效值的时期，用于逻辑合成阶段，布局和路由阶段，调试阶段，电路信息写入阶段的处理 可重新配置的设备等，以便使用要分配给行为级别描述中描述的变量的存储元件，并且实现最小化数据路径等的优化。 另外，在调试器和用于写入电路信息的写入装置中，上述活动信息用于执行不显示无效变量的任务，减少要保存到外部存储器的信息量的任务等。

公开(公告)号：US20070260847A1

公开(公告)日：2007-11-08

申请号：US11819976

申请日：2007-06-29

申请人： Toshirou Kitaoka ,  Taro Fujii ,  Kouichirou Furuta ,  Masato Motomura ,  Toru Awashima ,  Takao Toi

发明人： Toshirou Kitaoka ,  Taro Fujii ,  Kouichirou Furuta ,  Masato Motomura ,  Toru Awashima ,  Takao Toi

IPC分类号： G06F15/00

CPC分类号： G06F15/7867

摘要： A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.

摘要翻译： 可重构集成电路包括多个功能块和多个可编程开关，以可切换地连接包括在多个功能块中的功能块。 多个功能块各自包括至少一个操作单元或一个存储单元。 多个功能块各自包括连接到多个可编程开关中的至少一个的至少一个数据输入端口和连接到多个可编程开关中的至少一个的至少一个数据输出端口。 此外，包括在多个功能块中的至少一对功能块连接而不插入可编程开关，并且从包括在一对功能块之一中的直接输出端口输出的数据可被输入到包括的直接输入端口 在另一个功能块中。

公开(公告)号：US08032853B2

公开(公告)日：2011-10-04

申请号：US12379426

申请日：2009-02-20

申请人： Toru Awashima

发明人： Toru Awashima

IPC分类号： G06F17/50

CPC分类号： H03K19/17776 ,  H03K19/17748

摘要： A configuration information writing apparatus for writing configuration information defining a logical configuration of a logic circuit device into the logic circuit device to change the logical configuration thereof, the apparatus comprising: a difference extracting unit that acquires plural pieces of configuration information and extracts differences between each of the acquired plural pieces of configuration information; a differential relation generating unit that generates a differential relation indicating a relation of the differences between each of the plural pieces of configuration information based on the differences extracted by the difference extracting unit; and an order information generating unit that generates order information specifying an order of writing the configuration information from the relation of the differences indicated by the differential relation generated by the differential relation generating unit.

摘要翻译： 一种配置信息写入装置，用于将定义逻辑电路装置的逻辑配置的配置信息写入逻辑电路装置以改变其逻辑配置，该装置包括：差分提取单元，其获取多条配置信息并提取每个 获取的多条配置信息; 差分关系生成单元，基于由差分提取单元提取的差异生成表示多个构成信息中的每一个之间的差的关系的差分关系; 以及订单信息生成单元，根据由差分关系生成单元生成的差分关系所表示的差的关系，生成指定写入配置信息的顺序的顺序信息。

公开(公告)号：US08275973B2

公开(公告)日：2012-09-25

申请号：US12457649

申请日：2009-06-17

申请人： Takao Toi ,  Toru Awashima ,  Taro Fujii ,  Toshiro Kitaoka ,  Koichiro Furuta ,  Masato Motomura

发明人： Takao Toi ,  Toru Awashima ,  Taro Fujii ,  Toshiro Kitaoka ,  Koichiro Furuta ,  Masato Motomura

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F15/16

摘要： A reconfigurable device comprises a plurality of processing elements, a main memory unit that stores plural pieces of circuit configuration information, a cache unit that caches circuit configuration information forwarded to at least one of the processing elements from the main memory unit, and a cache control unit that controls forwarding of circuit configuration information from the cache unit to the processing element. The cache control unit selects circuit configuration information which must be forwarded to each processing element. When the selected circuit configuration information is not stored in the cache unit, the cache control unit reads out the circuit configuration information from the main memory unit, stores the read-out circuit configuration information in the cache unit, and sends forward the circuit configuration information to the processing element from the cache unit.

摘要翻译： 可重构装置包括多个处理元件，存储多条电路配置信息的主存储器单元，将从主存储器单元转发到至少一个处理元件的电路配置信息高速缓存的高速缓存单元，以及高速缓存控制 控制电路配置信息从高速缓存单元转发到处理单元的单元。 高速缓存控制单元选择必须转发给每个处理单元的电路配置信息。 当所选择的电路配置信息未被存储在高速缓存单元中时，高速缓存控制单元从主存储器单元读出电路配置信息，将读出的电路配置信息存储在高速缓存单元中，并且发送电路配置信息 从缓存单元到处理元件。

公开(公告)号：US08176451B2

公开(公告)日：2012-05-08

申请号：US12569043

申请日：2009-09-29

申请人： Takao Toi ,  Noritsugu Nakamura ,  Yoshinosuke Kato ,  Toru Awashima ,  Taro Fujii ,  Toshiro Kitaoka ,  Koichiro Furuta ,  Masato Motomura

发明人： Takao Toi ,  Noritsugu Nakamura ,  Yoshinosuke Kato ,  Toru Awashima ,  Taro Fujii ,  Toshiro Kitaoka ,  Koichiro Furuta ,  Masato Motomura

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

摘要翻译： 行为综​​合装置包括获取单元，调度单元和生成单元。 采集单元获取描述半导体集成电路的操作的行为级别描述。 调度单元将所获取的行为级别描述分为N级描述，并且进行调度，使得N级描述中的输入/输出操作和计算被流水线化。 生成单元基于N级描述和由调度单元执行的调度结果以分别对应于N级描述的级电路和控制可能的2N的状态控制电路来生成寄存器传送级别描述 -1级控制状态的半导体集成电路。 生成单元以禁止不需要操作的级电路的操作的方式生成寄存器传送级别描述。

公开(公告)号：US08151089B2

公开(公告)日：2012-04-03

申请号：US10694822

申请日：2003-10-29

申请人： Taro Fujii ,  Koichiro Furuta ,  Masato Motomura ,  Kenichiro Anjo ,  Yoshikazu Yabe ,  Toru Awashima ,  Takao Toi ,  Noritsugu Nakamura

发明人： Taro Fujii ,  Koichiro Furuta ,  Masato Motomura ,  Kenichiro Anjo ,  Yoshikazu Yabe ,  Toru Awashima ,  Takao Toi ,  Noritsugu Nakamura

IPC分类号： G06F15/00 ,  G06F15/76

CPC分类号： G06F15/8007

摘要： A multiplicity of processor elements that are arranged in rows and columns individually execute data processing in accordance with instruction codes that are individually set as data and supply event data as output. A state control unit is composed of a plurality of units that successively switch the instruction codes of the multiplicity of processor elements in accordance with a computer program and the event data, these state control units communicating with each other to realize linked operation as necessary. An event distributing means distributes event data to this plurality of state control units that intercommunicate to realize linked operation, whereby the plurality of state control units can realize linked operation to control a large-scale state transition.

摘要翻译： 排列成行和列的多个处理器元件根据单独设置为数据并提供事件数据作为输出的指令代码单独执行数据处理。 状态控制单元由多个单元组成，多个单元根据计算机程序和事件数据连续地切换多个处理器单元的指令代码，这些状态控制单元相互通信以根据需要实现链接操作。 事件分配装置将事件数据分配给相互通信的多个状态控制单元，以实现链接操作，由此多个状态控制单元可以实现链接操作以控制大规模状态转换。

公开(公告)号：US20110320996A1

公开(公告)日：2011-12-29

申请号：US13254335

申请日：2010-02-26

申请人： Toru Awashima ,  Yoshitaka Izawa

发明人： Toru Awashima ,  Yoshitaka Izawa

IPC分类号： G06F17/50

CPC分类号： G06F17/5031

摘要： A delay library generation apparatus (1) includes: a storage device (30) which stores architecture information (31) of a logic element array, layout data (35) of an overall programmable logic device, and a netlist (39) of the overall programmable logic device; a wiring route extraction unit (21) which refers to the storage device (30), and extracts wiring route information (33) regarding a wiring route section, based on the architecture information (31); an analyzing unit (23) which analyzes the layout data (35) of the overall programmable logic device, and extracts parameters of a parasitic element and a crosstalk caused between adjacent interconnections, the parasitic element and said crosstalk caused due to said global interconnection; a delay calculation unit (25) which calculates detailed delay data (37) based on the extracted parameters; and a delay library generation unit (27) which generates a delay library (41) of the programmable logic device, based on the wiring route information (33) and the detailed delay data (37).

摘要翻译： 延迟库生成装置（1）包括：存储装置（30），其存储逻辑元件阵列的架构信息（31），整体可编程逻辑装置的布局数据（35）和整体的网表（39） 可编程逻辑器件; 参考存储装置（30）的布线路径提取单元（21），基于架构信息（31）提取布线路径部分的布线路径信息（33）。 分析单元（23），其分析整个可编程逻辑器件的布局数据（35），并且提取在相邻互连之间引起的寄生元件和串扰的参数，由于所述全局互连造成的寄生元件和所述串扰; 延迟计算单元，其基于所提取的参数来计算详细的延迟数据; 以及基于布线路径信息（33）和详细延迟数据（37）生成可编程逻辑装置的延迟库（41）的延迟库生成单元（27）。

公开(公告)号：US08041925B2

公开(公告)日：2011-10-18

申请号：US11819976

申请日：2007-06-29

申请人： Toshirou Kitaoka ,  Taro Fujii ,  Kouichirou Furuta ,  Masato Motomura ,  Toru Awashima ,  Takao Toi

发明人： Toshirou Kitaoka ,  Taro Fujii ,  Kouichirou Furuta ,  Masato Motomura ,  Toru Awashima ,  Takao Toi

IPC分类号： G06F15/17

CPC分类号： G06F15/7867

摘要： A reconfigurable integrated circuit includes a plurality of function blocks and a plurality of programmable switches to switchably connect between function blocks included in the plurality of function blocks. The plurality of function blocks each includes at least one operation unit or one memory unit. The plurality of function blocks each includes at least one data input port connected to at least on of the plurality of programmable switches and at least one data output port connected to at least one of the plurality of programmable switches. Further, at least a pair of function blocks included in the plurality of function blocks is connected without intervening the programmable switch and data being output from a direct output port included in one of the pair of function blocks can be input to a direct input port included in the other of the pair of function blocks.

摘要翻译： 可重构集成电路包括多个功能块和多个可编程开关，以可切换地连接包括在多个功能块中的功能块。 多个功能块各自包括至少一个操作单元或一个存储单元。 多个功能块各自包括连接到多个可编程开关中的至少一个的至少一个数据输入端口和连接到多个可编程开关中的至少一个的至少一个数据输出端口。 此外，包括在多个功能块中的至少一对功能块连接而不插入可编程开关，并且从包括在一对功能块之一中的直接输出端口输出的数据可被输入到包括的直接输入端口 在另一个功能块中。

公开(公告)号：US20100083209A1

公开(公告)日：2010-04-01

申请号：US12569043

申请日：2009-09-29

申请人： Takao TOI ,  Noritsugu NAKAMURA ,  Yoshinosuke KATO ,  Toru AWASHIMA ,  Taro FUJII ,  Toshiro KITAOKA ,  Koichiro FURUTA ,  Masato MOTOMURA

发明人： Takao TOI ,  Noritsugu NAKAMURA ,  Yoshinosuke KATO ,  Toru AWASHIMA ,  Taro FUJII ,  Toshiro KITAOKA ,  Koichiro FURUTA ,  Masato MOTOMURA

IPC分类号： G06F17/50

CPC分类号： G06F17/505

摘要： A behavioral synthesis apparatus includes a acquisition unit, a scheduling unit and a generation unit. The acquisition unit acquires a behavioral level description describing an operation of a semiconductor integrated circuit. The scheduling unit separates the acquired behavioral level description into N stage descriptions, and makes a schedule in such a way that input/output operations and computations among the N stage descriptions are pipelined. The generation unit generates a register transfer level description based on the N stage descriptions and a result of scheduling performed by the scheduling unit in such a way as to form stage circuits respectively corresponding to the N stage descriptions and a state control circuit which controls possible 2N−1 stage control states of the semiconductor integrated circuit. The generation unit generates the register transfer level description in such a way as to inhibit the operation of a stage circuit which need not be operated.

摘要翻译： 行为综​​合装置包括获取单元，调度单元和生成单元。 采集单元获取描述半导体集成电路的操作的行为级别描述。 调度单元将所获取的行为级别描述分为N级描述，并且进行调度，使得N级描述中的输入/输出操作和计算被流水线化。 生成单元基于N级描述和由调度单元执行的调度结果以分别对应于N级描述的级电路和控制可能的2N的状态控制电路来生成寄存器传送级别描述 -1级控制状态的半导体集成电路。 生成单元以禁止不需要操作的级电路的操作的方式生成寄存器传送级别描述。