公开(公告)号：US4443887A

公开(公告)日：1984-04-17

申请号：US272831

申请日：1981-06-12

申请人： Takami Shiramizu

发明人： Takami Shiramizu

IPC分类号： G10H5/00 ,  H03K21/00 ,  H03K23/00 ,  H03K23/58 ,  H03K23/64 ,  H03K23/66 ,  H03K21/36

CPC分类号： H03K23/58 ,  H03K21/12 ,  H03K23/665

摘要： A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse. The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter.

摘要翻译： 分频电路包括具有多个半分频器的异步计数器，该多个分频器在多级中串联连接，其中主时钟信号被施加到初级的输入端，用于异步产生输出信号 其中异步计数器设置有预置数据n（n为整数）的半个分频器中的每一个，该预置数据是在施加负载脉冲时根据期望的分频比预设的，一致检测电路 检测从异步计数器提供的多个输出的一致性，以及提供有主时钟信号的分频输出信号和负载脉冲产生电路以及一致检测电路的输出信号，以产生分频输出信号 和负载脉冲。 分频输出信号和负载脉冲发生电路向异步计数器提供负载脉冲。

公开(公告)号：US4537108A

公开(公告)日：1985-08-27

申请号：US480128

申请日：1983-03-29

申请人： Takami Shiramizu

发明人： Takami Shiramizu

IPC分类号： G10H1/057 ,  G10H1/18 ,  G10H5/00 ,  G10H5/06 ,  G10H1/00

CPC分类号： G10H5/06 ,  Y10S84/11

摘要： An electronic musical instrument comprising a code generator responsive to the operation of each of the keys for generating a first code indicating a tone pitch and a second code indicating an octave associated with the operated key. A first variable frequency divider is presettable to a first count value as a function of the first code for counting master clock pulses supplied from an oscillator and generating a first divider output when the first count value is reached. A second variable frequency divider is presettable to a second count value as a function of the second code for counting the first divider output and generating a plurality of pulse trains having octave frequency relationship. A digital-to-analog converting means is provided for converting the pulse trains into an analog signal.

摘要翻译： 一种电子乐器，包括响应于每个键的操作的代码发生器，用于产生指示音调音调的第一代码和指示与所操作的键相关联的八度音阶的第二代码。 第一可变分频器被预置为第一计数值，作为用于对从振荡器提供的主时钟脉冲进行计数并在达到第一计数值时产生第一分频器输出的第一代码的函数。 第二可变分频器被预置为作为用于对第一分频器输出进行计数并产生具有八度频率关系的多个脉冲序列的第二代码的函数的第二计数值。 提供了一个数模转换装置，用于将脉冲串转换为模拟信号。