发明授权
- 专利标题: Frequency-dividing circuit
- 专利标题(中): 分频电路
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申请号: US272831申请日: 1981-06-12
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公开(公告)号: US4443887A公开(公告)日: 1984-04-17
- 发明人: Takami Shiramizu
- 申请人: Takami Shiramizu
- 申请人地址: JPX Yokohama
- 专利权人: Victor Company of Japan, Ltd.
- 当前专利权人: Victor Company of Japan, Ltd.
- 当前专利权人地址: JPX Yokohama
- 优先权: JPX55-81041 19800616
- 主分类号: G10H5/00
- IPC分类号: G10H5/00 ; H03K21/00 ; H03K23/00 ; H03K23/58 ; H03K23/64 ; H03K23/66 ; H03K21/36
摘要:
A frequency-dividing circuit comprises an asynchronous counter having a plurality of one-half frequency-dividers connected in series in a plurality of stages in which a master clock signal is applied to an input terminal of the initial stage, for asynchronously producing output signals of each of the one-half frequency-dividers, where the asynchronous counter is set with a preset data n (n is an integer) which is preset according to a desired frequency-dividing ratio when a load pulse is applied, a coincidence detection circuit for detecting the coincidence of a plurality of outputs supplied from the asynchronous counter, and a frequency-divided output signal and load pulse generation circuit supplied with the master clock signal and an output signal of the coincidence detection circuit, for generating a frequency-divided output signal and a load pulse. The frequency-divided output signal and load pulse generation circuit supplies a load pulse to the asynchronous counter.
公开/授权文献
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