公开(公告)号：US10510553B1

公开(公告)日：2019-12-17

申请号：US15993178

申请日：2018-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jack Kuo-Ping Kuo ,  Sheng-Liang Pan ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang

IPC分类号： H01L21/311 ,  H01L21/67 ,  H01J37/32

摘要： An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.

公开(公告)号：US20190371619A1

公开(公告)日：2019-12-05

申请号：US15993178

申请日：2018-05-30

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jack Kuo-Ping Kuo ,  Sheng-Liang Pan ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang

IPC分类号： H01L21/311 ,  H01L21/67 ,  H01J37/32

摘要： An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.

公开(公告)号：US11121025B2

公开(公告)日：2021-09-14

申请号：US16568622

申请日：2019-09-12

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Yun-Chang Hsu ,  Sheng-Liang Pan ,  Huan-Just Lin ,  Jack Kuo-Ping Kuo

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L29/417 ,  H01L23/532

摘要： A method of manufacturing a semiconductor device includes etching a via through a dielectric layer and an etch stop layer (ESL) to a source/drain contact, forming a recess in the top surface of the source/drain contact such that the top surface of the source/drain contact is concave, and forming an oxide liner on the sidewalls of the via. The oxide liner traps impurities left behind by the etching of the via through the dielectric layer and the ESL, wherein the etching, the forming the recess, and the forming the oxide liner are performed in a first chamber. The method further includes performing a pre-cleaning that removes the oxide liner and depositing a metal in the via.

公开(公告)号：US20200098588A1

公开(公告)日：2020-03-26

申请号：US16698398

申请日：2019-11-27

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Jack Kuo-Ping Kuo ,  Sheng-Liang Pan ,  Chia-Yang Hung ,  Jyu-Horng Shieh ,  Shu-Huei Suen ,  Syun-Ming Jang

IPC分类号： H01L21/311 ,  H01J37/32 ,  H01L21/67

摘要： An ashing process and device forms radicals of an ashing gas through a secondary reaction. A plasma is generated from a first gas, which is diffused through a first gas distribution plate (GDP). The plasma is diffused through a second GDP and a second gas is supplied below the second GDP. The first gas reacts with the second gas to energize the second gas. The energized second gas is used in ashing a resist layer from a substrate.