公开(公告)号：US12057468B2

公开(公告)日：2024-08-06

申请号：US17144121

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsien Kuo ,  Hon-Lin Huang ,  Han-Yi Lu ,  Ching-Wen Hsiao ,  Alexander Kalnitsky

IPC: H01F17/00 ,  H01F17/04 ,  H01F41/04 ,  H01L49/02

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F17/0033 ,  H01F17/04 ,  H01F41/046 ,  H01F2017/0086

Abstract: An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

公开(公告)号：US20220216295A1

公开(公告)日：2022-07-07

申请号：US17144121

申请日：2021-01-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsien Kuo ,  Hon-Lin Huang ,  Han-Yi Lu ,  Ching-Wen Hsiao ,  Alexander Kalnitsky

IPC: H01L49/02 ,  H01F17/00 ,  H01F41/04 ,  H01F17/04

Abstract: An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.

公开(公告)号：US20240347578A1

公开(公告)日：2024-10-17

申请号：US18751358

申请日：2024-06-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Hsien Kuo ,  Hon-Lin Huang ,  Han-Yi Lu ,  Ching-Wen Hsiao ,  Alexander Kalnitsky

IPC: H01F17/00 ,  H01F17/04 ,  H01F41/04

CPC classification number: H01L28/10 ,  H01F17/0013 ,  H01F17/0033 ,  H01F17/04 ,  H01F41/046 ,  H01F2017/0086

Abstract: A manufacturing method of a semiconductor device includes: forming a first dielectric layer on inductor traces, openings of the first dielectric layer exposing the inductor traces; disposing a buffer material on the first dielectric layer and the inductor traces in the openings; sequentially disposing an etch stop material and a ferromagnetic material on the buffer material; removing the ferromagnetic material from over the openings to form a core material layer covering a first area; removing the etch stop and buffer materials from the openings to form an etch stop layer and a buffer layer, where the etch stop and buffer layers cover a second area, the first area is smaller than and within the second area; forming a second dielectric layer on the first dielectric layer to embed the buffer, etch stop, and core material layers; and forming inductor vias extending through the first and second dielectric layers.