公开(公告)号：US10535568B2

公开(公告)日：2020-01-14

申请号：US16233243

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Tsao ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Yi-Huan Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/51

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.

公开(公告)号：US20190139837A1

公开(公告)日：2019-05-09

申请号：US16233243

申请日：2018-12-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Tsao ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Yi-Huan Chen

IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/66

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate including a multi-voltage device region. A first pair of source/drain regions are spaced apart from one another by a first channel region. A dielectric layer is disposed over the first channel region. A barrier layer is disposed over the dielectric layer. A fully silicided gate is disposed over the first channel region and is vertically separated from the semiconductor substrate by a work function tuning layer. The work function tuning layer separates the fully silicided gate from the barrier layer.

公开(公告)号：US10177043B1

公开(公告)日：2019-01-08

申请号：US15793163

申请日：2017-10-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Han Tsao ,  Chii-Ming Wu ,  Cheng-Yuan Tsai ,  Yi-Huan Chen

IPC: H01L21/8238 ,  H01L29/66 ,  H01L29/49 ,  H01L27/092

Abstract: A method for manufacturing multi-voltage devices is provided. The method includes forming a pair of logic gate stacks in a logic region of a semiconductor substrate and a pair of device gate stacks in a multi-voltage device region. The pair of logic gate stacks and the pair of device gate stacks include first dummy gate material. The pair of device gate stacks also includes a work function tuning layer. The method further includes depositing second dummy gate material over the pair of logic gate stacks. The first dummy gate material and the second dummy gate material from over a first logic gate stack of the pair of logic gate stacks are replaced with an n-type material. The first dummy gate material and the second dummy gate material from over a second logic gate stack of the pair of logic gate stacks are replaced with a p-type material.