公开(公告)号：US10510572B2

公开(公告)日：2019-12-17

申请号：US16449452

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

IPC: H01L21/677

Abstract: A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

公开(公告)号：US20200098613A1

公开(公告)日：2020-03-26

申请号：US16677626

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

IPC: H01L21/677

Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

公开(公告)号：US10978329B2

公开(公告)日：2021-04-13

申请号：US16677626

申请日：2019-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

IPC: H01L21/677

Abstract: A method for wafer pod handling includes at least the following steps. A wafer pod is moved into a load chamber by conveying the wafer pod to the load chamber via one side of a track and removing a cover of the load chamber via an opposing side of the track. The wafer pod that is inside the load chamber is coupled to a port of a platform that is linked to the load chamber. A wafer to be processed is moved from the wafer pod and out of the load chamber to the platform for performing a semiconductor process. Other methods for wafer pod handling are also provided.

公开(公告)号：US20170207109A1

公开(公告)日：2017-07-20

申请号：US14996231

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

IPC: H01L21/673

CPC classification number: H01L21/67775 ,  H01L21/67772

Abstract: A semiconductor processing station comprises a platform and a load port, wherein the platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and is configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. A semiconductor process and a method of operating a semiconductor processing station are also provided.

公开(公告)号：US20190311930A1

公开(公告)日：2019-10-10

申请号：US16449452

申请日：2019-06-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

IPC: H01L21/677

Abstract: A semiconductor processing station including a platform, a load port, and a carrier transport track is provided. The platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover, and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. The carrier transport track has a bottom side configured to open the load chamber.

公开(公告)号：US10332769B2

公开(公告)日：2019-06-25

申请号：US14996231

申请日：2016-01-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： You-Hua Chou ,  Chih-Wei Huang ,  Kuo-Sheng Chuang ,  Cheng-Chung Chien

IPC: H01L21/677

Abstract: A semiconductor processing station comprises a platform and a load port, wherein the platform includes an intake/outtake port and a plurality of processing modules. The load port includes a load chamber, a movable cover and a carrier transfer module. The load chamber communicates with the intake/outtake port and has a load opening at its top end for receiving a transport carrier within the load chamber. The movable cover is disposed at the load opening and is configured to seal the load opening. The carrier transfer module is configured to transfer the transport carrier to the intake/outtake port. A semiconductor process and a method of operating a semiconductor processing station are also provided.

公开(公告)号：US10189143B2

公开(公告)日：2019-01-29

申请号：US15158529

申请日：2016-05-18

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chi-Hao Huang ,  Hsuan-Pang Liu ,  Yuan-Chun Sie ,  Pinyen Lin ,  Cheng-Chung Chien

IPC: B24B37/20 ,  B24D18/00 ,  B24B37/22 ,  B24B37/26

Abstract: A polishing pad for a chemical-mechanical polishing apparatus includes a first support layer and a polishing layer. The polishing layer is present on the first support layer. The polishing layer has a top surface that faces away from the first support layer and at least one first cavity that is buried at least beneath the top surface of the polishing layer.