公开(公告)号：US20220085515A1

公开(公告)日：2022-03-17

申请号：US17418237

申请日：2019-12-18

Applicant: THALES

Inventor： Adrien GLISE ,  Isabelle LE ROY-NANEIX ,  Stefan VARAULT ,  Grégoire PILLET ,  Christian RENARD

IPC: H01Q15/14 ,  H01Q1/52 ,  H01Q19/02 ,  H01Q17/00 ,  H01Q15/00

Abstract: An array antenna (A) in a medium (M) comprises a plurality of radiating elements (ERT) ensuring the transition between the antenna and the medium, the reflectivity of each element depending on a parameter, the reflectivity of a first element being close to that of the medium, the reflectivity of a last element being close to that of the antenna, the reflectivity parameter of the elements varying from one element to the next. A method comprises calculation of a path equal to the sum of the variations of the reflectivity from one element to the next element, optimization of the variation of the reflectivity parameter so that equivalent radar cross-section of the antenna is the lowest possible or the antenna best observes the radiation objectives, determination of the different elements as a function of said parameter, and simulation of the overall reflectivity and/or of the radiation of the antenna.

公开(公告)号：US20240014564A1

公开(公告)日：2024-01-11

申请号：US18348090

申请日：2023-07-06

Applicant: THALES ,  UNIVERSITÉ DE BORDEAUX ,  INSTITUT POLYTECHNIQUE DE BORDEAUX ,  Centre national de la recherche scientifique

Inventor： Timothée LE GALL ,  Anthony GHIOTTO ,  Gwenaël MORVAN ,  Stefan VARAULT ,  Bruno LOUIS ,  Grégoire PILLET

IPC: H01Q9/04 ,  H01Q1/48 ,  H01Q21/24

CPC classification number: H01Q9/045 ,  H01Q1/48 ,  H01Q21/24

Abstract: The elementary antenna 1 includes: two cross-shaped slots 32, 33 defining four half-slots; for each half-slot, excitation striplines 41, 42, the first stripline 41 being connected to a first via 61 and the second stripline 42 being connected to a second via 62; an integrated circuit 70 delivering a plurality of ports; for each half-slot, tracks for feeding the strips, the first track 51 running from a first port 71 to the first via 61 and the second track 52 running from a second port 72 to the second via 62, the first and second ports being two successive ports of the integrated circuit, differentially connected to a transmitter/receiver channel by first and second power lines situated inside the integrated circuit, the lines and tracks running so that there is no crossing of the respective routes thereof.