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公开(公告)号：US20230308055A1
公开(公告)日：2023-09-28
申请号：US17897958
申请日：2022-08-29
Applicant: Texas Instruments Incorporated
Inventor： Kunal Karanjkar , Venkata Ramanan R , Srinivasa BS Chakravarthy , Per Torstein Roine
CPC classification number: H03F1/26 , H03F1/304 , H03F2200/375
Abstract: An example device includes: switch circuitry configured to: connect, in a first state based on a control signal, a first switch input to a first switch output and a second switch input to a second switch output; and connect, in a second state based on the control signal, the first switch input to the second switch output and the second switch input to the first switch output; an operational amplifier configured to: generate, in response to the control signal, a first voltage based on a gain and the connections in the first state; and generate, in response to the control signal, a second voltage based on the gain and the connections in the second state; and an Analog to Digital Converter (ADC) configured to convert the first voltage and the second voltage into a digital value based on a multiplication of the input voltage and the gain.
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公开(公告)号：US11444612B2
公开(公告)日：2022-09-13
申请号：US17223097
申请日：2021-04-06
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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公开(公告)号：US20210167775A1
公开(公告)日：2021-06-03
申请号：US17169638
申请日：2021-02-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin AGARWAL , Kunal Suresh KARANJKAR , Venkata Ramanan R
IPC: H03K17/693 , H03K17/10 , H03K17/00 , H03F3/72
Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
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公开(公告)号：US20200321952A1
公开(公告)日：2020-10-08
申请号：US16378526
申请日：2019-04-08
Applicant: Texas Instruments Incorporated
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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公开(公告)号：US11955964B2
公开(公告)日：2024-04-09
申请号：US17169638
申请日：2021-02-08
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Suresh Karanjkar , Venkata Ramanan R
IPC: H03K17/693 , H03F3/72 , H03K17/00 , H03K17/10
CPC classification number: H03K17/693 , H03F3/72 , H03K17/005 , H03K17/102
Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
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Patent Agency Ranking
公开(公告)号：US11848678B2
公开(公告)日：2023-12-19
申请号：US17931557
申请日：2022-09-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
CPC classification number: H03K5/2481 , H03F1/0205 , H03F3/45179
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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公开(公告)号：US10917090B1
公开(公告)日：2021-02-09
申请号：US16700444
申请日：2019-12-02
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Kunal Suresh Karanjkar , Venkata Ramanan R
IPC: H03K17/693 , H03K17/10 , H03K17/00 , H03F3/72
Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
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公开(公告)号：US20240213981A1
公开(公告)日：2024-06-27
申请号：US18599361
申请日：2024-03-08
Applicant: Texas Instruments Incorporated
Inventor： Nitin AGARWAL , Kunal Suresh KARANJKAR , Venkata Ramanan R
IPC: H03K17/693 , H03F3/72 , H03K17/00 , H03K17/10
CPC classification number: H03K17/693 , H03F3/72 , H03K17/005 , H03K17/102
Abstract: A circuit includes a first switch assembly having a first input node and a first output node, and a second switch assembly having a second input node and a second output node. The circuit further includes a third switch assembly an operational amplifier, and a buffer. The third switch assembly has a third input node and a third output node. The third input node is coupled to the second output node, and the third output node is coupled to the first output node. The buffer has a buffer input and a buffer output. The buffer input is coupled to an input stage of the operational amplifier. The buffer output is coupled to the third switch assembly.
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公开(公告)号：US20230006663A1
公开(公告)日：2023-01-05
申请号：US17931557
申请日：2022-09-13
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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公开(公告)号：US10972086B2
公开(公告)日：2021-04-06
申请号：US16378526
申请日：2019-04-08
Applicant: Texas Instruments Incorporated
Inventor： Nitin Agarwal , Venkat Ramakrishna Saripalli , Venkata Ramanan R
Abstract: In described examples, an amplifier can be arranged to generate a first stage output signal in response to an input signal. The input signal can be coupled to control a first current coupled from a first current source through a common node to generate the first stage output signal. A replica circuit can be arranged to generate a replica load signal in response to the input signal and in response to current received from the common node. A current switch can be arranged to selectively couple a second current from a second current source to the common node in response to the replica load signal.
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