公开(公告)号：US20210175859A1

公开(公告)日：2021-06-10

申请号：US16708660

申请日：2019-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Steven Graham BRANTLEY ,  Munaf Hussain SHAIK ,  Bhuvanesh RADHAKRISHNAN KULASEKARAN

IPC: H03F1/34 ,  H03F3/213

Abstract: An amplifier circuit includes a high-voltage output stage. The high-voltage output stage includes an output terminal, a high-side output circuit, a low-side output circuit, and a feedback circuit. The high-side output circuit sources current to the output terminal, and includes a high-side input transistor, a first high-side cascode transistor coupled to the high-side input transistor, and a second high-side cascode transistor coupled to the first high-side cascode transistor and the output terminal. The low-side output circuit sinks current from the output terminal, and includes a low-side input transistor, a first low-side cascode transistor coupled to the low-side input transistor, and a second low-side cascode transistor coupled to the first low-side cascode transistor and the output terminal. The feedback circuit is configured to bias the second high-side cascode transistor and the second low-side cascode transistor based on a sense voltage generated by the high-side output circuit or the low-side output circuit.

公开(公告)号：US20190190471A1

公开(公告)日：2019-06-20

申请号：US15848700

申请日：2017-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Martijn Fridus SNOEIJ ,  Steven Graham BRANTLEY

IPC: H03F3/45 ,  H03F3/16

CPC classification number: H03F3/45089 ,  H03F3/165 ,  H03F3/45071 ,  H03F3/45085 ,  H03F3/45094 ,  H03F3/45183 ,  H03F3/45188 ,  H03F2203/45061 ,  H03F2203/45134 ,  H03F2203/45248

Abstract: An operational amplifier includes an input stage configured to receive a first input voltage and a second input voltage and a slew boost circuit coupled to the input stage and configured to selectively increase current through the input stage. The operational amplifier also includes an output stage coupled to the input stage and configured to generate an output voltage, and a slew boost disable circuit configured to assert a control signal to the slew boost circuit to disable the slew boost circuit. The slew boost circuit is disabled when both: the first input voltage being more than a first threshold voltage different from the second input voltage and the output voltage failing to change by more than a second threshold rate.