公开(公告)号：US20240291632A1

公开(公告)日：2024-08-29

申请号：US18174395

申请日：2023-02-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jaiganesh BALAKRISHNAN ,  Kandalla KRISHNA ,  Aravind VIJAYAKUMAR ,  Goutham RAMESH

IPC: H04L7/04 ,  H04L1/00 ,  H04L7/00

CPC classification number: H04L7/04 ,  H04L1/0057 ,  H04L7/0079

Abstract: A receiver includes: a PHY layer, and a processor coupled to the PHY layer. The processor is configured to: receive a set of data bits from the PHY layer; compare the set of data bits to a sync header pattern; determine a mismatch metric responsive to the comparison and to an adjustable scaling factor, and execute link synchronization operations based on the mismatch metric.