公开(公告)号：US20190280649A1

公开(公告)日：2019-09-12

申请号：US16214179

申请日：2018-12-10

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Jayawardan JANARDHANAN ,  Eric Paul LINDGREN ,  Henry YAO

IPC: H03D3/24 ,  H03L7/081 ,  H03L7/099 ,  H04J3/06

Abstract: A circuit includes a time-to-digital converter (TDC) to produce an output signal that is a function of a time difference between a first input clock to the TDC and a second input clock to the TDC. A first delay line is also included to add a time delay to a third clock to produce the first input clock. A pseudo random binary sequence generator generates a pseudo random binary bit sequence to be used to vary the amount of time delay added by the first delay line to the third clock.

公开(公告)号：US20190280695A1

公开(公告)日：2019-09-12

申请号：US16232893

申请日：2018-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eric Paul LINDGREN ,  Arvind SRIDHAR ,  Jayawardan JANARDHANAN

IPC: H03L7/085

Abstract: A selection circuit receives a plurality of reference clocks. The selection circuit is controlled by a control signal to output one of the plurality of reference clocks. A phase-locked loop couples to an output of the selection circuit and uses the selected reference clock for phase locking an output clock. A plurality of reference clock window detector circuits is included. Each reference clock window detector circuit receives a separate reference clock. Each reference clock window detector circuit asserts an error signal responsive to an early reference clock edge error in which the reference clock window detector circuit detects a reference clock edge before expiration of an early time window. Further, each reference clock window detector circuit asserts the error signal responsive to a late reference clock edge error in which the reference clock window detector circuit detects a reference clock edge after expiration of a late time window.

公开(公告)号：US20190288694A1

公开(公告)日：2019-09-19

申请号：US16226938

申请日：2018-12-20

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Sinjeet Dhanvantray PAREKH ,  Eric Paul LINDGREN ,  Christopher Andrew SCHELL ,  Jayawardan JANARDHANAN

IPC: H03L7/07 ,  H03K5/13 ,  H03L7/093

Abstract: A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.