公开(公告)号：US20050136599A1

公开(公告)日：2005-06-23

申请号：US11020217

申请日：2004-12-27

申请人： Stephane Martel ,  Yan Riopel ,  Sebastien Michel ,  Luc Ouellet

发明人： Stephane Martel ,  Yan Riopel ,  Sebastien Michel ,  Luc Ouellet

IPC分类号： H01L21/8249 ,  H01L21/336

CPC分类号： H01L21/8249

摘要： A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of the following steps: (1) applying a first mask and forming at least one N-well in said p-type material therethrough; (2) applying a second mask and forming an active region therethrough; (3) applying a third mask and forming a p-type field region therethrough; (4) applying a fourth mask and forming a gate oxide therethrough; (5) applying a fifth mask and carrying out a p-type implantation therethrough; (6) applying a sixth mask and forming polysilicon gate regions therethrough; (7) applying a seventh mask and forming a p-base region therethrough; (8) applying an eighth mask and forming a N-extended region therethrough; (9) applying a ninth mask and forming a p-top region therethrough; (10) applying a tenth mask and carrying out an N+ implant therethrough; (11) applying an eleventh mask and carrying out a P+ implant therethrough; (12) applying a twelfth mask and forming contacts therethrough; (13) applying a thirteenth mask and depositing a metal layer therethrough; (14) applying a fourteenth mask and forming vias therethrough; (15) applying a fifteenth mask and depositing a metal layer therethrough; and (16) applying a sixteenth mask and forming a passivation layer therethrough. Up to any three of mask steps 4, 7, 8, and 9 may be omitted depending on the type of integrated circuit.

摘要翻译： 描述了制造集成电路的方法，其中掩模步骤的顺序被施加到p型材料的衬底或外延层。 该顺序包括以下步骤：（1）施加第一掩模并在所述p型材料中形成至少一个N阱; （2）施加第二掩模并形成通过其的有源区域; （3）施加第三掩模并形成p型场区; （4）施加第四掩模并形成栅极氧化物; （5）施加第五掩模并进行p型注入; （6）施加第六掩模并形成多晶硅栅极区域; （7）施加第七掩模并形成通过其的p基区域; （8）施加第八掩模并形成N延伸区域; （9）施加第九掩模并形成通过其的p顶部区域; （10）施加第十掩模并且通过其移动N +植入物; （11）施加第十一掩模并且通过其进行P +植入; （12）施加第十二掩模并形成触点; （13）施加第十三掩模并通过其沉积金属层; （14）施加第十四掩模并形成通孔; （15）施加第十五掩模并通过其沉积金属层; 和（16）施加第十六掩模并形成钝化层。 根据集成电路的类型，可以省略任何三个掩模步骤4,7,8和9。

公开(公告)号：US07341905B2

公开(公告)日：2008-03-11

申请号：US11020217

申请日：2004-12-27

申请人： Stephane Martel ,  Yan Riopel ,  Sebastien Michel ,  Luc Ouellet

发明人： Stephane Martel ,  Yan Riopel ,  Sebastien Michel ,  Luc Ouellet

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/8238

CPC分类号： H01L21/8249

摘要： A process for making an integrated circuit is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence consists of sixteen specific mask steps that permit a variety of bipolar/CMOS/DMOS devices to be fabricated. The mask steps include (1) forming at least one N-well in the p-type material, (2) forming an active region, forming a p-type field region, (4) forming a gate oxide, (5) carrying out a p-type implantation, (6) forming polysilicon gate regions, (7) forming a p-base region, (8) forming a N-extended region, (9) forming a p-top region, 10) carrying out an N+ implant, (11) carrying out a P+ implant, (12) forming contacts, (13) depositing a metal layer, (14) forming vias, (15) depositing a metal layer therethrough, and (16) forming a passivation layer. Up to any three of mask steps (4), (7), (8), and (9) may be omitted depending on the type of integrated circuit.

摘要翻译： 描述了制造集成电路的方法，其中掩模步骤的顺序被施加到p型材料的衬底或外延层。 该序列由16个特定的掩模步骤组成，允许制造各种双极/ CMOS / DMOS器件。 掩模步骤包括（1）在p型材料中形成至少一个N阱，（2）形成有源区，形成p型场区，（4）形成栅极氧化物，（5） （6）形成多晶硅栅极区，（7）形成p基区，（8）形成N延伸区，（9）形成p顶区，10）进行N + （11）进行P +注入，（12）形成触点，（13）沉积金属层，（14）形成通孔，（15）沉积金属层，以及（16）形成钝化层。 根据集成电路的类型，可以省略任何三个掩模步骤（4），（7），（8）和（9）。

公开(公告)号：US06849491B2

公开(公告)日：2005-02-01

申请号：US09964472

申请日：2001-09-28

申请人： Stephane Martel ,  Yan Riopel ,  Sebastien Michel ,  Luc Ouellet

发明人： Stephane Martel ,  Yan Riopel ,  Sebastien Michel ,  Luc Ouellet

IPC分类号： H01L21/8249 ,  H01L21/00 ,  H01L21/8238 ,  H01L21/84

CPC分类号： H01L21/8249

摘要： A process for making a integrated circuits of different typed is described wherein sequence of mask steps is applied to a substrate or epitaxial layer of p-type material. The sequence is chosen from a predefined common set of mask steps according to the particular type of integrated circuit to be fabricated. In this way, various types of integrated circuit can be fabricated in a most efficient manner.

摘要翻译： 描述了制造不同类型的集成电路的工艺，其中掩模步骤的顺序被施加到p型材料的衬底或外延层。 根据要制造的集成电路的特定类型，从预定义的一组掩模步骤中选择该序列。 以这种方式，可以以最有效的方式制造各种类型的集成电路。