公开(公告)号：US20190393898A1

公开(公告)日：2019-12-26

申请号：US16474568

申请日：2018-02-27

申请人： Sony Semiconductor Solutions Corporation ,  Sony Corporation

发明人： Seiji KOBAYASHI ,  Masanori SATO ,  Nabil LOGHIN ,  Toshihiro FUJIKI ,  Ryoji IKEGAYA ,  Hiroyuki KAMATA ,  Yusuke YONEYAMA ,  Kimiya KATO ,  Akira ENDO ,  Sawako KIRIYAMA ,  Hiroyuki MITA ,  Hideshi MOTOYAMA ,  Hiroshi AOKI ,  Daisuke KAWAKAMI

IPC分类号： H03M13/19 ,  H03M13/11 ,  H04L1/08

摘要： LDPC coding is executed using a check matrix of an LDPC code whose code length is 736 bits and whose code rate is 1/4, and modulation is executed using a repetition unit that has an LDPC code obtained by the LDPC coding, repeatedly arranged therein. The LDPC code includes information bits and parity bits, the check matrix includes an information matrix portion corresponding to the information bits and a parity matrix portion corresponding to the parity bits, the parity matrix portion has a stepwise structure, the information matrix portion is indicated by a check matrix initial value table, and the check matrix initial value table is a predetermined table indicating positions of elements of “1” of the information matrix portion for each eight columns. This technique is applicable to, for example, information transmission using the LDPC code.