公开(公告)号：US07870342B2

公开(公告)日：2011-01-11

申请号：US10646289

申请日：2003-08-21

申请人： Son Ho ,  Kevin Tonthat ,  Hai Van ,  Joseph Sheredy

发明人： Son Ho ,  Kevin Tonthat ,  Hai Van ,  Joseph Sheredy

IPC分类号： G06F12/00

CPC分类号： G06F12/0862 ,  G06F2212/2022

摘要： A memory storage system includes a line cache including a plurality of pages. A first central processing unit (CPU) accesses data stored in the pages of the line cache. A first memory device stores data that is loaded into the line cache when a miss occurs. After an initial miss, the line cache prevents additional misses as long as the first CPU is addressing sequential memory locations of the first memory device. When the miss occurs, n pages of the line cache are loaded with data from sequential locations in the first memory device, wherein n is greater than one. When the CPU requests data from an mth page of the n pages in the line cache, wherein m is greater than one and less than or equal to n, the line cache loads p additional pages with data from sequential locations in the first memory device.

摘要翻译： 存储器存储系统包括包括多页的行高速缓存。 第一中央处理单元（CPU）访问存储在行高速缓存的页面中的数据。 第一存储器设备存储当发生未命中时加载到行高速缓存中的数据。 在初次缺席之后，只要第一个CPU正在寻址第一个存储器设备的顺序存储器位置，该行高速缓存即可防止额外的漏洞。 当出现未命中时，线缓存的n页被加载有来自第一存储器件中的顺序位置的数据，其中n大于1。 当CPU从行缓存中的n页的第m页请求数据时，其中m大于1且小于或等于n，行缓存使用来自第一存储器设备中的顺序位置的数据加载p个附加页。

公开(公告)号：US20050021912A1

公开(公告)日：2005-01-27

申请号：US10646289

申请日：2003-08-21

申请人： Son Ho ,  Kevin Tonthat ,  Hai-Hoa Van ,  Joseph Sheredy

发明人： Son Ho ,  Kevin Tonthat ,  Hai-Hoa Van ,  Joseph Sheredy

IPC分类号： G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F2212/2022

摘要： A memory storage system includes a line cache including a plurality of pages. A first central processing unit (CPU) accesses data stored in the pages of the line cache. A first memory device stores data that is loaded into the line cache when a miss occurs. After an initial miss, the line cache prevents additional misses as long as the first CPU is addressing sequential memory locations of the first memory device. When the miss occurs, n pages of the line cache are loaded with data from sequential locations in the first memory device, wherein n is greater than one. When the CPU requests data from an mth page of the n pages in the line cache, wherein m is greater than one and less than or equal to n, the line cache loads p additional pages with data from sequential locations in the first memory device.

摘要翻译： 存储器存储系统包括包括多页的行高速缓存。 第一中央处理单元（CPU）访问存储在行高速缓存的页面中的数据。 第一存储器设备存储当发生未命中时加载到行高速缓存中的数据。 在初次缺席之后，只要第一个CPU正在寻址第一个存储器设备的顺序存储器位置，该行高速缓存即可防止额外的漏洞。 当出现未命中时，线缓存的n页被加载有来自第一存储器件中的顺序位置的数据，其中n大于1。 当CPU从行高速缓存中的n页的第m页的数据请求时，其中m大于1且小于或等于n，行缓存使用来自第一个 存储设备。

公开(公告)号：US07250751B2

公开(公告)日：2007-07-31

申请号：US11243697

申请日：2005-10-05

申请人： Saeed Azimi ,  Son Ho

发明人： Saeed Azimi ,  Son Ho

IPC分类号： G01R31/28

CPC分类号： G01R31/3004 ,  G01R31/31716

摘要： A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

公开(公告)号：US20070063726A1

公开(公告)日：2007-03-22

申请号：US11601170

申请日：2006-11-17

申请人： Saeed Azimi ,  Son Ho

发明人： Saeed Azimi ,  Son Ho

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G01R31/31716

摘要： A method of making and testing a system on chip (SOC) comprises providing an integrated system test (IST) module in each one of a plurality of SOC components. At least one of the SOC components communicates with an external interface and at least one other of the SOC components. The method includes receiving test configuration data, transmitting test result data, and transmitting and receiving application data via the external interface. The method includes using at least one of the IST modules to receive the test configuration data and configure the IST modules to test the plurality of SOC components.

摘要翻译： 一种制造和测试片上系统（SOC）的方法包括在多个SOC组件中的每一个中提供集成系统测试（IST）模块。 SOC组件中的至少一个与外部接口和SOC组件中的至少另一个通信。 该方法包括接收测试配置数据，发送测试结果数据，以及通过外部接口发送和接收应用数据。 该方法包括使用至少一个IST模块来接收测试配置数据并配置IST模块以测试多个SOC组件。

公开(公告)号：US08074135B1

公开(公告)日：2011-12-06

申请号：US12500245

申请日：2009-07-09

申请人： Saeed Azimi ,  Son Ho

发明人： Saeed Azimi ,  Son Ho

IPC分类号： G06F11/00

CPC分类号： G01R31/31705 ,  G01R31/318572 ,  G06F11/2236

摘要： An integrated circuit includes an embedded processor. An embedded in-circuit emulator is located within the embedded processor. The embedded in-circuit emulator performs a test on the integrated circuit. The embedded in-circuit emulator generates a testing result based on the test on the integrated circuit. Trace logic to generate trace data based on the testing result, the trace data being in a parallel format. A serializer is located on the integrated circuit. The serializer converts the parallel format of the trace data into a serial format. The serializer serially outputs the trace data in the serial format from the integrated circuit.

摘要翻译： 集成电路包括嵌入式处理器。 嵌入式在线仿真器位于嵌入式处理器内。 嵌入式在线仿真器对集成电路进行测试。 嵌入式在线仿真器基于集成电路上的测试产生测试结果。 跟踪逻辑根据测试结果生成跟踪数据，跟踪数据采用并行格式。 串行器位于集成电路上。 串行器将跟踪数据的并行格式转换为串行格式。 串行器从集成电路串行输出串行格式的跟踪数据。

公开(公告)号：US07590911B1

公开(公告)日：2009-09-15

申请号：US11130995

申请日：2005-05-17

申请人： Saeed Azimi ,  Son Ho ,  Daniel Smathers

发明人： Saeed Azimi ,  Son Ho ,  Daniel Smathers

IPC分类号： G01R31/28

CPC分类号： G01R31/31705 ,  G01R31/318572 ,  G06F11/2236

摘要： An integrated circuit includes a first deserializer that deserializes serial data containing at least one of test instructions and/or data in a first format. A monitor module communicates with the first deserializer and interprets the test instructions and data using the first format. A frame capture module receives test results according to the interpreted test instructions and data. A first control module communicates with the frame capture module and generates first format control data. The frame capture module packages the test results and the first format control data into frames. A first serializer serializes the frames.

摘要翻译： 集成电路包括反序列化包含第一格式的测试指令和/或数据中的至少一个的串行数据的第一解串器。 监视器模块与第一解串器通信，并使用第一格式解释测试指令和数据。 帧捕获模块根据解释的测试指令和数据接收测试结果。 第一控制模块与帧捕获模块通信并产生第一格式控制数据。 帧捕获模块将测试结果和第一格式控制数据打包成帧。 第一个串行器串行化帧。

公开(公告)号：US20070024309A1

公开(公告)日：2007-02-01

申请号：US11243697

申请日：2005-10-05

申请人： Saeed Azimi ,  Son Ho

发明人： Saeed Azimi ,  Son Ho

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G01R31/31716

摘要： A system comprises a printed circuit board (PCB). A system on chip (SOC) mounted on the PCB includes a controller that communicates with an external interface that receives test configuration data, transmits test result data, and transmits and receives application data. At least one chip mounted to the PCB, wherein the SOC comprises an SOC component that includes an integrated system test (IST) module. At least one chip comprises a chip component that includes an integrated system test (IST) module. At least one of the SOC component and the chip component, communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing at least one of the SOC component and the chip component.

摘要翻译： 系统包括印刷电路板（PCB）。 安装在PCB上的片上系统（SOC）包括与接收测试配置数据的外部接口通信的控制器，发送测试结果数据以及发送和接收应用数据。 安装到PCB的至少一个芯片，其中所述SOC包括包括集成系统测试（IST）模块的SOC组件。 至少一个芯片包括包括集成系统测试（IST）模块的芯片组件。 SOC组件和芯片组件中的至少一个与控制器通信。 至少有一个IST模块是主IST模块，接收测试配置数据并配置IST模块，用于测试至少一个SOC组件和芯片组件。

公开(公告)号：US20070024308A1

公开(公告)日：2007-02-01

申请号：US11243661

申请日：2005-10-05

申请人： Saeed Azimi ,  Son Ho

发明人： Saeed Azimi ,  Son Ho

IPC分类号： G01R31/26

CPC分类号： G01R31/3004 ,  G01R31/31716

摘要： A system on chip (SOC), comprises an external interface that receives test configuration data, transmits test result data, and that transmits and receives application data. A plurality of SOC components, each including an integrated system test (IST) module, wherein at least one of the SOC components includes a controller that communicates with the external interface. At least one of the plurality of SOC components communicates with the controller. At least one of the IST modules is a master IST module that receives the test configuration data and configures the IST modules for testing the plurality of SOC components.

摘要翻译： 片上系统（SOC）包括接收测试配置数据，发送测试结果数据以及发送和接收应用数据的外部接口。 多个SOC部件，每个都包括集成系统测试（IST）模块，其中至少一个SOC部件包括与外部接口通信的控制器。 多个SOC部件中的至少一个与控制器通信。 至少有一个IST模块是主IST模块，它接收测试配置数据并配置IST模块以测试多个SOC组件。

公开(公告)号：US20070024271A1

公开(公告)日：2007-02-01

申请号：US11189458

申请日：2005-07-26

申请人： Saeed Azimi ,  Son Ho

发明人： Saeed Azimi ,  Son Ho

IPC分类号： G01R31/28

CPC分类号： G11B20/182 ,  G01R31/3004 ,  G01R31/31716 ,  G01R31/31717 ,  G11B5/455

摘要： A hard disk drive system includes an external interface that receives test configuration data, that transmits test result data, and that transmits and receives application data. The hard disk drive system includes a system on chip (SOC) that includes a controller and a read/write channel that communicates with the controller and that includes an integrated system test (IST) module that communicates with the external interface. A memory module communicates with the SOC and includes memory and an IST module. The hard disk drive system includes a spindle/voice coil motor driver module that includes an IST module. At least one of the IST modules is a master IST module that receives the test configuration data and that configures the IST modules for testing at least one of the controller, the read/write channel, and the memory module.

摘要翻译： 硬盘驱动器系统包括接收测试配置数据，发送测试结果数据以及发送和接收应用数据的外部接口。 硬盘驱动器系统包括片上系统（SOC），其包括与控制器通信的控制器和读/写通道，并且包括与外部接口通信的集成系统测试（IST）模块。 存储器模块与SOC通信并且包括存储器和IST模块。 硬盘驱动器系统包括主轴/音圈电机驱动器模块，其包括IST模块。 至少有一个IST模块是主IST模块，它接收测试配置数据，并配置IST模块，用于测试至少一个控制器，读/写通道和内存模块。

公开(公告)号：US08356223B1

公开(公告)日：2013-01-15

申请号：US13446627

申请日：2012-04-13

申请人： Saeed Azimi ,  Son Ho ,  Daniel Smathers

发明人： Saeed Azimi ,  Son Ho ,  Daniel Smathers

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/31705 ,  G01R31/318572 ,  G06F11/2236

摘要： A system including a frame capture module, a serializer, and a deserializer. The frame capture module is configured to receive, from a device under test, data corresponding to test results, and package the data into first data frames. The serializer is configured serialize the first data frames to form serial messages that include serialized data. The serializer includes i) a first serial link configured to output the serial messages according to a first clock domain, and ii) a second serial link configured to output the serial messages according to a second clock domain. The deserializer is configured to deserialize the serial messages received on the first serial link and the second serial link to form second data frames.