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公开(公告)号：US12081251B2
公开(公告)日：2024-09-03
申请号：US18057054
申请日：2022-11-18
申请人： Socionext Inc.
发明人： Kenta Aruga , Takashi Miyazaki , Daisuke Kimura , Yasuhiro Majima , Shunichiro Masaki , Shunsuke Hirano
CPC分类号： H04B1/10 , H04L27/0008
摘要： A processing circuit includes: a clock generating circuit configured to generate, based on a reference clock signal and a frequency division ratio, a first clock signal; a frequency dividing and delay circuit configured to generate a second clock signal to have a first phase difference with the reference clock signal by dividing the frequency of the first clock signal and delaying the first clock signal based on a phase shift set signal and the frequency division ratio; an analog-to-digital converter circuit configured to convert an analog signal into a digital signal based on the first clock signal and a conversion trigger signal indicating a sampling period and a conversion period; and a control circuit configured to generate the conversion trigger signal to have the same cycle as the second clock signal based on the frequency division ratio and the first clock signal.
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公开(公告)号：US11265043B2
公开(公告)日：2022-03-01
申请号：US16806891
申请日：2020-03-02
申请人： SOCIONEXT INC.
发明人： Shunichiro Masaki
摘要： A communication circuit includes a first buffer configured to output a signal indicative of a first logic state or a second logic state, a signal in which the first logic state and the second logic state are defined being input to the first buffer, a second buffer configured to output a signal indicative of any one of the first logic state, the second logic state, and a third logic state, the signal output from the first buffer being input to the second buffer, and a monitoring circuit configured to monitor a logic state indicated by the signal output from the first buffer and cause the second buffer, in a case where the logic state does not change during a first period, to output the signal indicative of the third logic state.
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