公开(公告)号：US20220406708A1

公开(公告)日：2022-12-22

申请号：US17360793

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Thomas C. Fowler ,  Jerome T. Wenske

IPC: H01L23/522 ,  H01L21/71 ,  H01L49/02

Abstract: An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

公开(公告)号：US11626366B2

公开(公告)日：2023-04-11

申请号：US17360793

申请日：2021-06-28

Applicant: Silicon Laboratories Inc.

Inventor： Thomas C. Fowler ,  Jerome T. Wenske

IPC: H01L23/522 ,  H01L21/71 ,  H01L23/00 ,  H01L49/02

Abstract: An integrated circuit includes a capacitor with a bottom conductive plate and a top conductive plate. A passivation layer is disposed above the top conductive plate. An intermetal dielectric layer is disposed between the bottom conductive plate and the top conductive plate and is formed of a first dielectric material. Shield layers are disposed between the top conductive plate and above the intermetal dielectric layer and extend horizontally to at least past guard rings. The shield layers include a dielectric layer formed of dielectric material having a dielectric constant greater than the material of the intermetal dielectric layer. The shield layers include horizontally offset trenches to stop horizontal flow of current in the shield layers. The offset ensures there is no vertical path from the passivation layer to lower/ground potentials through the shield layers.

公开(公告)号：US20210202375A1

公开(公告)日：2021-07-01

申请号：US16728224

申请日：2019-12-27

Applicant: Silicon Laboratories Inc.

Inventor： Thomas C. Fowler ,  Jerome T. Wenske ,  Ahsanul Islam ,  Dan B. Kasha

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/532 ,  H01L23/528 ,  H01L49/02

Abstract: An isolation capacitor structure reduces the likelihood of breakdown in the passivation layers by physically re-shaping or dividing the top plate of the isolation capacitor into two segments. In that way, the electric field is driven down and away from the passivation surfaces. One embodiment utilizes a series capacitor formed by the top metal plate of the capacitor and an additional “top hat” plate above the top metal plate that redirects the fields into the main isolation capacitor. Vias may be included between the top hat plate and the top metal plate. Another approach reshapes the top plate to have an integrated top hat structure and achieves similar results of directing charge down and away from the passivation layer surface breakdown paths.