公开(公告)号：US20200152802A1

公开(公告)日：2020-05-14

申请号：US16619532

申请日：2018-06-04

Applicant: Sharp Kabushiki Kaisha

Inventor： Yujiro TAKEDA ,  Hiroshi MATSUKIZONO ,  Akihiro ODA ,  Shogo MURASHIGE ,  Kohhei TANAKA

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/24 ,  H01L29/66

Abstract: An active matrix substrate of an embodiment of the present invention includes a substrate and a plurality of oxide semiconductor TFTs supported on the substrate. Each oxide semiconductor TFT includes a lower gate electrode provided on the substrate, a gate insulating layer covering the lower gate electrode, an oxide semiconductor layer provided on the gate insulating layer, a source electrode which is in contact with the source contact region of the oxide semiconductor layer, a drain electrode which is in contact with the drain contact region of the oxide semiconductor layer, an insulating layer covering the oxide semiconductor layer, the source electrode and the drain electrode, and an upper gate electrode provided on the insulating layer. When viewed in a normal direction of the substrate, the upper gate electrode does not overlap a first electrode which is one of the source electrode and the drain electrode, and a second electrode which is the other of the source electrode and the drain electrode does not overlap the lower gate electrode.

公开(公告)号：US20210135013A1

公开(公告)日：2021-05-06

申请号：US16473638

申请日：2017-12-15

Applicant: Sharp Kabushiki Kaisha

Inventor： Shinji NAKAJIMA ,  Hirohiko NISHIKI ,  Yujiro TAKEDA ,  Shogo MURASHIGE

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/26

Abstract: A semiconductor device includes a substrate and an oxide semiconductor TFT supported by the substrate. The oxide semiconductor TFT includes an oxide semiconductor layer containing In, Ga, and Zn, a gate electrode, a gate insulating layer formed between the gate electrode and the oxide semiconductor layer, and a source electrode and a drain electrode that are in contact with the oxide semiconductor layer. The oxide semiconductor layer has a layered structure that includes a first layer, a second layer, and an intermediate transition layer disposed between the first layer and the second layer, and the first layer is disposed closer to the gate insulating layer side than the second layer. The first layer and the second layer have different compositions, and the intermediate transition layer has a continuously changing composition from the first layer side toward the second layer side.

公开(公告)号：US20190113813A1

公开(公告)日：2019-04-18

申请号：US16088851

申请日：2017-03-24

Applicant: Sharp Kabushiki Kaisha

Inventor： Tohru OKABE ,  Hirohiko NISHIKI ,  Shinji NAKAJIMA ,  Izumi ISHIDA ,  Shogo MURASHIGE

IPC: G02F1/1362 ,  G02F1/1365 ,  H01L29/786 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/02

Abstract: Provided are an active-matrix substrate, a method for manufacturing the same, and a display device, which render it possible to inhibit electrostatic discharge from occurring during the process of manufacturing a display panel and suppress manufacturing cost.An IGZO film, which is positioned between a silicon oxide film included in a gate insulating film and an etch-stop layer, is annealed at 200 to 350° C. after a passivation film for protecting a TFT is formed. As a result, the passivation film is annealed, and the IGZO film is changed from a conductor to a semiconductor. Consequently, it is not only possible to suppress the occurrence of ESD, but also possible to eliminate the need to sever an electrostatic discharge prevention circuit from a display panel, resulting in a reduced cost of manufacturing a display device.

公开(公告)号：US20200243568A1

公开(公告)日：2020-07-30

申请号：US16491229

申请日：2018-03-02

Applicant: Sharp Kabushiki Kaisha

Inventor： Akihiro ODA ,  Yujiro TAKEDA ,  Shogo MURASHIGE ,  Hiroshi MATSUKIZONO

IPC: H01L27/12 ,  H01L29/786 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66 ,  H01L21/02

Abstract: An active matrix substrate includes: a substrate (1); a peripheral circuit including a plurality of first TFTs (10); and a plurality of second TFTs (20), wherein each of the first and second TFTs (10, 20) includes: a gate electrode (3A, 3B); a gate insulating layer (5); an oxide semiconductor layer (7A, 7B) including a channel region (7Ac, 7Bc), a source contact region (7As, 7Bs) and a drain contact region (7Ad, 7Bd), wherein the source contact region and the drain contact region are located on opposite sides of the channel region; a source electrode (8A, 8B) that is in contact with the source contact region and a drain electrode (9A, 9B) that is in contact with the drain contact region; the oxide semiconductor layer of the first TFTs and the second TFTs is formed from the same oxide semiconductor film; a carrier concentration in the channel regions (7Ac) of the first TETs is higher than a carrier concentration in the channel regions (7Bc) of the second TETs.

公开(公告)号：US20190103052A1

公开(公告)日：2019-04-04

申请号：US16086321

申请日：2017-03-27

Applicant: Sharp Kabushiki Kaisha

Inventor： Tohru OKABE ,  Hirohiko NISHIKI ,  Shinji NAKAJIMA ,  Izumi ISHIDA ,  Shogo MURASHIGE

IPC: G09G3/32 ,  H01L27/32 ,  H01L51/52

CPC classification number: G09G3/32 ,  G02B26/023 ,  G09F9/30 ,  G09F9/37 ,  H01L27/3272 ,  H01L27/3276 ,  H01L51/5203

Abstract: A wiring delay is prevented or reduced by lowering a wiring resistance without making a wire wider. The present invention includes: a light blocking film (102); a light-transmitting film (106); and a first wiring layer (105A) which serves as part of a wire configured to electrically control an amount of transmitted light for each pixel, the first wiring layer (105A) being provided over the light blocking film (102), and the light-transmitting film (106) being provided over the first wiring layer (105A) so as to cover a side surface of the first wiring layer.

公开(公告)号：US20150303307A1

公开(公告)日：2015-10-22

申请号：US14432997

申请日：2013-09-30

Applicant: Sharp Kabushiki Kaisha

Inventor： Takeshi HARA ,  Hirohiko NISHIKI ,  Izumi ISHIDA ,  Shogo MURASHIGE

IPC: H01L29/786 ,  G02F1/1362 ,  G02F1/1368 ,  H01L29/24 ,  H01L27/12

CPC classification number: H01L29/7869 ,  G02F1/136286 ,  G02F1/1368 ,  H01L21/28008 ,  H01L27/1248 ,  H01L29/24 ,  H01L29/78606

Abstract: This semiconductor device is provided with: a semiconductor film that comprises an oxide semiconductor, and includes a channel region; a first inorganic insulating film formed on the semiconductor film; a first organic insulating film formed on the first inorganic insulating film; and an inorganic film group. The inorganic film group has: a first electrode comprising an inorganic conductive film formed on the first organic insulating film; a second inorganic insulating film formed on the first electrode; and a second electrode that comprises an inorganic conductive film formed on the second inorganic insulating film, and is electrically connected to the semiconductor film via openings formed in such a manner as to penetrate the first inorganic insulating film, the first organic insulating film, the first electrode and the second inorganic insulating film. The first organic insulating film is disposed between the first inorganic insulating film and the inorganic film group.

Abstract translation: 该半导体装置设置有：包括氧化物半导体的半导体膜，并且包括沟道区; 形成在半导体膜上的第一无机绝缘膜; 形成在第一无机绝缘膜上的第一有机绝缘膜; 和无机膜组。 无机膜组具有：第一电极，其包含形成在第一有机绝缘膜上的无机导电膜; 形成在第一电极上的第二无机绝缘膜; 以及第二电极，其包括形成在所述第二无机绝缘膜上的无机导电膜，并且通过形成为穿过所述第一无机绝缘膜，所述第一有机绝缘膜，所述第一无机绝缘膜的开口电连接到所述半导体膜 电极和第二无机绝缘膜。 第一有机绝缘膜设置在第一无机绝缘膜和无机膜组之间。