公开(公告)号：US20070208914A1

公开(公告)日：2007-09-06

申请号：US11682540

申请日：2007-03-06

Applicant: Sen-Huang Tang ,  Yi-Shu Chang ,  Yu-Zoung Chou ,  Chien-Hua Hsieh

Inventor： Sen-Huang Tang ,  Yi-Shu Chang ,  Yu-Zoung Chou ,  Chien-Hua Hsieh

IPC: G06F13/00

CPC classification number: G06F13/4022

Abstract: A memory access apparatus is disclosed. The apparatus comprising: a memory access module, having a first interface and a second interface; a first bus, coupled to the first interface; a first memory, coupled to the first bus, for storing a first data; a second bus, coupled to the second interface; and a second memory, coupled to the second bus, for storing a second data; wherein said memory access module accesses said first memory or said second memory or both according to the using statuses of said first bus and said second bus.

Abstract translation: 公开了一种存储器访问装置。 该装置包括：具有第一接口和第二接口的存储器访问模块; 第一个总线，耦合到第一个接口; 第一存储器，耦合到第一总线，用于存储第一数据; 第二总线，耦合到第二接口; 以及耦合到所述第二总线的用于存储第二数据的第二存储器; 其中所述存储器访问模块根据所述第一总线和所述第二总线的使用状态访问所述第一存储器或所述第二存储器或两者。

公开(公告)号：US20050156650A1

公开(公告)日：2005-07-21

申请号：US11035088

申请日：2005-01-13

Applicant: Sen-Huang Tang ,  Yi-Shu Chang

Inventor： Sen-Huang Tang ,  Yi-Shu Chang

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: The invention is related to a method and an apparatus for generating an output clock. The method comprises: measuring a reference clock according to a free-run clock to produce a counter signal in a normal mode; suspending the reference clock; and generating the output clock according to the counter signal and the free-run clock in a power-saving mode.

Abstract translation: 本发明涉及一种用于产生输出时钟的方法和装置。 该方法包括：根据自由运行时钟测量参考时钟以产生正常模式的计数器信号; 暂停参考时钟; 以及在省电模式下根据计数器信号和自由运行时钟产生输出时钟。

公开(公告)号：US20070194826A1

公开(公告)日：2007-08-23

申请号：US11675084

申请日：2007-02-15

Applicant: Sen-Huang Tang ,  Yi-Shu Chang

Inventor： Sen-Huang Tang ,  Yi-Shu Chang

IPC: H03L7/00

CPC classification number: H03L7/0814 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00247

Abstract: The present invention discloses a circuit capable of self-correcting delay time that includes a clock generating unit for generating a clock signal, a processing unit for producing a counter enable signal according to a reference clock, and a counting unit for receiving the counter enable signal and using the clock signal to count the reference clock for producing a count value, and the count value is returned to the processing unit for performing an analysis to obtain a delay time. The present invention can effectively overcome the shortcomings of the prior art that requires a delay circuit to make corrections one by one, and thus the invention can greatly save the time, manpower, and cost incurred.

Abstract translation: 本发明公开了一种能够进行自校正延迟时间的电路，包括用于产生时钟信号的时钟产生单元，用于根据参考时钟产生计数器使能信号的处理单元，以及用于接收计数器使能信号的计数单元 并且使用时钟信号对用于产生计数值的参考时钟进行计数，并且将计数值返回到处理单元以进行分析以获得延迟时间。 本发明可以有效地克服需要延迟电路逐个进行校正的现有技术的缺点，从而可以大大节省时间，人力和成本。

公开(公告)号：US07106118B2

公开(公告)日：2006-09-12

申请号：US11035088

申请日：2005-01-13

Applicant: Sen-Huang Tang ,  Yi-Shu Chang

Inventor： Sen-Huang Tang ,  Yi-Shu Chang

IPC: G06F1/04

CPC classification number: G06F1/04

Abstract: The invention is related to a method and an apparatus for generating an output clock. The method comprises: measuring a reference clock according to a free-run clock to produce a counter signal in a normal mode; suspending the reference clock; and generating the output clock according to the counter signal and the free-run clock in a power-saving mode.

Abstract translation: 本发明涉及一种用于产生输出时钟的方法和装置。 该方法包括：根据自由运行时钟测量参考时钟以产生正常模式的计数器信号; 暂停参考时钟; 以及在省电模式下根据计数器信号和自由运行时钟产生输出时钟。

公开(公告)号：US07583324B2

公开(公告)日：2009-09-01

申请号：US11161819

申请日：2005-08-17

Applicant: Ming-Jane Hsieh ,  Yi-Shu Chang ,  Te-Ming Kuo ,  Shi-Wei Chen

Inventor： Ming-Jane Hsieh ,  Yi-Shu Chang ,  Te-Ming Kuo ,  Shi-Wei Chen

IPC: H04N9/64 ,  H04N5/445

CPC classification number: H04N5/45 ,  H04N5/4401 ,  H04N5/44508 ,  H04N21/42646 ,  H04N21/4316 ,  H04N21/4347

Abstract: A video processing method utilized in a video data processing device for processing video data is disclosed. The video data includes at least a first video data set, and the video data processing device has a memory and a video decoder. The method includes utilizing the video decoder to decode the video data for generating a display data set, driving the video decoder to select a specific video data set from the first video data set wherein the display data set does not have display data corresponding to the specific video data set, and utilizing the memory to store the display data.

Abstract translation: 公开了用于处理视频数据的视频数据处理装置中使用的视频处理方法。 视频数据至少包括第一视频数据组，并且视频数据处理装置具有存储器和视频解码器。 该方法包括利用视频解码器来解码用于产生显示数据集的视频数据，驱动视频解码器从第一视频数据集中选择特定的视频数据集，其中显示数据集不具有对应于具体的显示数据的显示数据 视频数据集，并利用存储器来存储显示数据。

公开(公告)号：US07492413B2

公开(公告)日：2009-02-17

申请号：US11142932

申请日：2005-06-02

Applicant: Chia-Hao Hsiung ,  Yi-Shu Chang ,  Ting-Yang Chang

Inventor： Chia-Hao Hsiung ,  Yi-Shu Chang ,  Ting-Yang Chang

IPC: H04N7/00

CPC classification number: H04N7/035 ,  H04L7/0331 ,  H04N5/44 ,  H04N21/435 ,  H04N21/8126

Abstract: A VBI receiver and method is disclosed. The receiver includes an over-sampling circuit, a transition detector, a data selector, and a data output device. The over-sampling circuit is for over-sampling VBI data and outputting and over-sampled signal. The transition detector is for detecting the transition of the over-sampled signal and outputting a transition signal representing the transition position. The data selector is for recording the transition signal and outputting a position signal according to the transition signal and at least a previous transition signal. The data output device outputs digital output data from the over-sampled signal according to the position signal.

Abstract translation: 公开了一种VBI接收机和方法。 接收机包括过采样电路，转换检测器，数据选择器和数据输出装置。 过采样电路用于对VBI数据进行过采样并输出和过采样信号。 转换检测器用于检测过采样信号的转变并输出表示转换位置的转换信号。 数据选择器用于记录转换信号并根据转换信号和至少先前的转换信号输出位置信号。 数据输出装置根据位置信号从过采样信号输出数字输出数据。

公开(公告)号：US20080055487A1

公开(公告)日：2008-03-06

申请号：US11896242

申请日：2007-08-30

Applicant: Yi-Shu Chang

Inventor： Yi-Shu Chang

IPC: H04N5/455

CPC classification number: H04N5/50 ,  H04N5/455 ,  H04N21/4263 ,  H04N21/4384

Abstract: The invention provides a digital television tuner having at least two brances that receive a radio frequency signal, wherein the radio frequency signal carries M channels (M is a positive integer). A target image data is generated in real time since at least one of the branches pre-extracts the image compression data of the next channel to be switched to.

Abstract translation: 本发明提供了一种数字电视调谐器，具有至少两个接收射频信号的分支，其中射频信号携带M个信道（M是正整数）。 目标图像数据是实时生成的，因为至少一个分支预先提取要切换到的下一个信道的图像压缩数据。

公开(公告)号：US07194097B2

公开(公告)日：2007-03-20

申请号：US10441045

申请日：2003-05-20

Applicant: Chu-Ting Su ,  Yi-Shu Chang ,  Jul-Cheng Huang ,  Wen-Chi Wang

Inventor： Chu-Ting Su ,  Yi-Shu Chang ,  Jul-Cheng Huang ,  Wen-Chi Wang

IPC: H03F21/00

CPC classification number: H03F3/68 ,  Y10T307/696

Abstract: An Audio Codec which comprises a power selecting circuit an audio compiler circuit and a control amplifier circuit. The power selecting circuit receives at least a primary power source and an auxiliary power source and outputs a working power selected from the power sources. The auxiliary power source is selected and output to the control amplifier circuit only when the computer is at a power-off status. When the computer is power-on, the primary power source will be selected and output to both the audio compiler circuit and the control amplifier circuit. Therefore, the Audio Codec of the present invention only needs one set of internally furnished control amplifier circuit to both operate on the normal power-on status and perform the Power OFF CD function.

Abstract translation: 音频编解码器，其包括音频编译器电路和控制放大器电路的功率选择电路。 功率选择电路至少接收主电源和辅助电源，并输出从电源选择的工作电源。 只有当计算机处于断电状态时，辅助电源被选择并输出到控制放大器电路。 当计算机上电时，主电源将被选择并输出到音频编译器电路和控制放大器电路。 因此，本发明的音频编解码器仅需要一套内部布置的控制放大器电路，以在正常的开机状态下操作并执行断电CD功能。

公开(公告)号：US07071702B2

公开(公告)日：2006-07-04

申请号：US10776536

申请日：2004-02-12

Applicant: Ming-Jane Hsieh ,  Chuting Su ,  Yi-Shu Chang ,  Ming-Lih Lin

Inventor： Ming-Jane Hsieh ,  Chuting Su ,  Yi-Shu Chang ,  Ming-Lih Lin

IPC: G01R31/04 ,  G01R19/00 ,  H01H31/02 ,  H04M1/00

CPC classification number: H04R5/04 ,  H04B1/20 ,  H04R29/00 ,  H04R2420/05

Abstract: A multi-jack detector for detecting states of a plurality of jacks. Each jack comprises a first switch having a first normally closed terminal and a first output terminal. The multi-jack detector comprises a plurality of bias resistors each coupled to one of the first output terminals, respectively; a control unit for determining the states of the plurality of jacks; wherein the first normally closed terminals are commonly coupled to a first node and the control unit determines the states of the plurality of jacks according to a voltage at the first node. Because the voltage at the first node is different for each state of the jacks, the detector can detects the states of the jacks using a single I/O pin.

Abstract translation: 一种用于检测多个插孔的状态的多插孔检测器。 每个插孔包括具有第一常闭端子和第一输出端子的第一开关。 多插座检测器包括分别耦合到第一输出端之一的多个偏置电阻器; 用于确定所述多个插孔的状态的控制单元; 其中所述第一常闭端子共同耦合到第一节点，并且所述控制单元根据所述第一节点处的电压来确定所述多个插孔的状态。 因为第一节点处的电压对于插孔的每个状态是不同的，所以检测器可以使用单个I / O引脚来检测插座的状态。

公开(公告)号：US07831751B2

公开(公告)日：2010-11-09

申请号：US11306190

申请日：2005-12-19

Applicant: Yi-Shu Chang ,  Wen-Che Wu ,  Wen-Jui Lin

Inventor： Yi-Shu Chang ,  Wen-Che Wu ,  Wen-Jui Lin

IPC: G06F13/10

CPC classification number: G06F8/61 ,  G06F8/654

Abstract: A system for programming at least a controller chip is disclosed. The system includes a programming apparatus and at least a programmable device mounted on the programming apparatus. The programming apparatus has at least a first connection interface and a micro-controller. The programmable device has the monitor controller chip mounted thereon and a second connection interface coupled between the first connection interface and the controller chip. The micro-controller controls the programming of the controller chip.

Abstract translation: 公开了一种用于至少编程控制器芯片的系统。 该系统包括编程设备和至少一个安装在编程设备上的可编程设备。 编程设备至少具有第一连接接口和微控制器。 可编程装置具有安装在其上的监视器控制器芯片和耦合在第一连接接口和控制器芯片之间的第二连接接口。 微控制器控制控制器芯片的编程。