公开(公告)号：US20220206950A1

公开(公告)日：2022-06-30

申请号：US17134790

申请日：2020-12-28

Applicant: ADVANCED MICRO DEVICES, INC. ,  SAMSUNG ELECTRONICS CO., LTD.

Inventor： Fataneh GHODRAT ,  Stephen W. SOMOGYI ,  Zhenhong LIU

IPC: G06F12/0891 ,  G06F12/0831 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics pipeline includes a texture cache having cache lines that are partitioned into a plurality of subsets. The graphics pipeline also includes one or more compute units that selectively generates a miss request for a first subset of the plurality of subsets of a cache line in the texture cache in response to a cache miss for a memory access request to an address associated with the first subset of the cache line. In some embodiments, the cache lines are partitioned into a first sector and a second sector. The compute units generate miss requests for the first sector, and bypass generating miss requests for the second sector, in response to cache misses for memory access requests received during a request cycle being in the first sector.

公开(公告)号：US20220083473A1

公开(公告)日：2022-03-17

申请号：US17175607

申请日：2021-02-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Anshujit SHARMA ,  Sushant KONDGULI ,  Zhenhong LIU ,  Wilson Wai Lun FUNG ,  Arun RADHAKRISHNAN ,  Wayne YAMAMOTO

IPC: G06F12/0875 ,  G06F12/02 ,  G06T1/20 ,  G06T1/60

Abstract: A graphics processing unit (GPU) includes a table located in a memory of the GPU and a cache hierarchy. The table contains an address of inactive data in a cache hierarchy of the GPU in which the inactive data is associated with an intermediate render target. The cache hierarchy is responsive to an eviction event by discarding the inactive data from the cache hierarchy without performing a writeback to a system memory associated with the GPU based on the address of the inactive data being contained in the table. The cache hierarchy may obtain the address of the inactive data from the table, and the inactive data may be located in a last-level cache of the cache hierarchy. In one embodiment, the address of inactive data in a cache hierarchy of the GPU includes a range of addresses for the inactive data.