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公开(公告)号：US20240267138A1
公开(公告)日：2024-08-08
申请号：US18431087
申请日：2024-02-02
Applicant: Samsung Electronics Co., Ltd.
Inventor： Yungeun NAM , Hobin SONG , Hyogyuem RHEW , Jaehyun PARK , Jongshin SHIN
CPC classification number: H04B17/297 , H04B17/19 , H04B17/295
Abstract: A transceiver according to an aspect of the inventive concepts may include a transmitter, a first receiver pad configured to receive a first external voltage, a second receiver pad configured to receive a second external voltage, a receiver configured to generate a test target signal based on the first external voltage and the second external voltage, and a digital logic configured to perform a loopback test on a reception path of a data signal by transmitting the data signal and receiving the test target signal.
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公开(公告)号：US20220190869A1
公开(公告)日：2022-06-16
申请号：US17384991
申请日：2021-07-26
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Younwoong CHUNG , Yungeun NAM , Jongshin SHIN
Abstract: Disclosed is a transceiver which includes a logic circuit that generates parallel transmission data in response to a first test mode signal or a second test mode signal, a serializer that converts the parallel transmission data into serial transmission data, a driver that outputs the serial transmission data through transmission pads, an analog circuit that receives serial reception data through reception pads, a deserializer that converts the serial reception data into parallel reception data, a plurality of test switches switched in response to the first test mode signal, and a test circuit that is electrically connected to the analog circuit through the plurality of test switches and outputs serial post data corresponding to the serial transmission data to the analog circuit.
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公开(公告)号：US20230130236A1
公开(公告)日：2023-04-27
申请号：US17972869
申请日：2022-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hobin SONG , Yungeun NAM , Byeonggyu PARK , Jaehyun PARK , Hajung PARK , Junhan BAE
Abstract: A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.
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公开(公告)号：US20220014195A1
公开(公告)日：2022-01-13
申请号：US17160888
申请日：2021-01-28
Applicant: Samsung Electronics Co., Ltd.
Inventor： Hwang Ho CHOI , Yungeun NAM , Sodam JU
IPC: H03K19/0185 , H04L25/02 , G11C11/4093 , G11C7/10
Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node, supplying a third power supply voltage, through a first variable resistor and connected to a fourth power supply node, supplying a fourth power supply voltage, lower than the third power supply node, through a second variable resistor.
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